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STEL-2000A 2 features/benefits .............................................................................................................. ......................... 3 block diagram.................................................................................................................. ............................ 3 package outline................................................................................................................ .......................... 4 pin configuration.............................................................................................................. ........................ 4 general description ............................................................................................................ ..................... 5 functional blocks.............................................................................................................. ....................... 7 transmit and receive clock generator blocks.................................................................................. 7 input and output processor blocks .............................................................................................. ...... 7 differential encoder block..................................................................................................... ............... 7 transmitter pn code generator block............................................................................................ ... 7 bpsk/qpsk modulator block...................................................................................................... ....... 8 frequency control register and nco block ..................................................................................... 8 downconverter block............................................................................................................ ................ 8 receiver pn code register and pn matched filter blocks............................................................. 9 power detector block ........................................................................................................... ................. 10 symbol tracking processor block................................................................................................ ........ 11 differential demodulator block ................................................................................................. ......... 11 frequency discriminator and loop filter block ............................................................................... 12 input signals.................................................................................................................. ................................ 14 output signals................................................................................................................. ............................. 18 transmitter and receiver test points .......................................................................................... 2 0 control registers .............................................................................................................. ........................ 21 downconverter registers........................................................................................................ .............. 21 pn matched filter registers.................................................................................................... ............. 22 power estimator registers...................................................................................................... .............. 23 acquisition and tracking processor registers .................................................................................. 2 4 demodulator registers.......................................................................................................... ................ 27 output processor control registers............................................................................................. ....... 29 transmit control registers..................................................................................................... .............. 31 register setting sequence ........................................................................................................ 33 decimal, hex and binary address equivalents....................................................................... 34 register summary ............................................................................................................... ........................ 35 electrical characteristics ..................................................................................................... ............ 36 absolute maximum ratings.................................................................................................... 36 recommended operating conditions ............................................................................. 36 d.c. characteristics........................................................................................................... ......... 36 transmitter input/output timing .................................................................................... 37 receiver input/output timing.............................................................................................. 38 microprocessor interface timing ..................................................................................... 39 appendix i: theory of operation ............................................................................................... ....... 40 digital downconversion ......................................................................................................... .............. 40 using the STEL-2000A with a single adc in direct i.f. sampling mode ............................... 40 using the STEL-2000A with two adcs in quadrature sampling mode ................................ 43 differential demodulation ...................................................................................................... ............. 44 bpsk demodulation ......................................................................................................... ................ 44 qpsk demodulation ......................................................................................................... ............... 44 frequency error generation..................................................................................................... ............ 45 using the modulator in the STEL-2000A transmitter...................................................................... 46 appendix ii: typical application .............................................................................................. ......... 48 .com .com .com .com 4 .com u datasheet
3 STEL-2000A features n complete direct sequence spread spectrum burst transceiver in a single cmos i.c. n programmable functionality supports many different operational modes n supports pn chip rate of over 11 mchips/sec. in transmit and receive modes (STEL-2000A+45 only) n acquires within one symbol duration using digital pn matched filter n two independent pn sequences, each up to 64 chips long, for distinct processing of the acquisition/preamble symbol and subsequent data symbols n power management features n optional spectral whitening code generation n full or half duplex operation n 100-pin pqfp packaging benefits n high performance and high reliability with reduced manufacturing costs n ideal for a wide range of wireless applications including data acquisition systems, transaction systems and wireless local area networks (wlans) n supports data rates up to 2.048 mbps in compliance with fcc regulations (STEL-2000A+45 only) n fast response and very low overhead when operating in burst modes n allows high processing gain to maximize the acquisition probability, then reduced code length for increased data rate n low power consumption n randomizes data to meet regulatory requirements n permits dual frequency (frequency division duplex) or single frequency (time division duplex) operation n small footprint, surface mount block diagram (figure 1) a tx cl o ck gener- at o r o ut put dat a processor di f f er- ential enco der t x pn co de g enerat o rs qpsk mo du- lator bit clock symbol clock chip clock tx ifc lk nco do w n co nvert er matched filter power det ect o r symbol t racki ng processor rx cl o ck g ener- at o r symbol clock corrected bit clock corrected symbol clock f req uency di scri mi nat o r & loop filter sin cos f req uency co nt ro l register 2x chip clock di f f erent i al demo dul at o r rx pn co de reg i st ers chip clock rxmabrt mnco en mtxen mrxen mfld dat a 7-0 addr 6-0 co nt ro l & p inter- face reset wr csel txifclk txin txbitpls txtrkpls t xmchp txifout 7-0 txiout txqout t xchppl s t xacq pl s rxiin 7-0 rxqin 7-0 rxi f cl k rxmsmpl rxmdet rxo ut rxiout rxqout rxdrdy rxsympls rxact i ve txactive tx overlay co de g enerat o r rx overlay co de g enerat o r txtest rxt est 7-0 oen rxifclk i nput dat a processor .com .com .com .com 4 .com u datasheet
STEL-2000A 4 package outline (figure 2) top view 0.941" 0.010" 0.742" 0.005" 0.487" 0.003" 0.705" 0.010" 0.11" nom. 0.122" max. 0.014" 0.002" 0.0256" 0.002" 0.031" 0.005" 0.009" 0.005" pin 1 identifier 1 80 50 30 81 51 31 100 detail of pins package style: 100-pin pqfp. thermal characteristics: q ja = 41 c/w (STEL-2000A+45), q ja = 68 c/w (STEL-2000A+20) pin configuration 1v dd 2 rxqin 0 3 rxqin 1 4 rxqin 2 5 rxqin 3 6 rxqin 4 7 rxqin 5 8 rxqin 6 9 rxqin 7 10 mrxen 11 v dd 12 rxifclk 13 v ss 14 txifclk 15 v ss 16 reset eeeeee 17 mtxen 18 txin 19 txmchp 20 data 0 21 data 1 22 data 2 23 data 3 24 data 4 25 data 5 26 data 6 27 data 7 28 wr eee 29 csel eeeee 30 v ss 31 v dd 32 addr 0 33 addr 1 34 addr 2 35 addr 3 36 addr 4 37 addr 5 38 addr 6 39 v ss 40 v dd 41 rxtest 7 42 rxtest 6 43 rxtest 5 44 rxtest 4 45 rxtest 3 46 rxtest 2 47 rxtest 1 48 rxtest 0 49 oen eeee 50 v ss 51 v dd 52 rxsympls 53 rxsplpls 54 rxdrdy eeeeeeeee 55 rxqout 56 rxiout 57 rxout 58 i.c. 59 txtest 60 txacqpls 61 txtrkpls 62 txchppls 63 txbitpls 64 v ss 65 v dd 66 txifout 7 67 txifout 6 68 txifout 5 69 txifout 4 70 txifout 3 71 txifout 2 72 txifout 1 73 txifout 0 74 v ss 75 v dd 76 txqout 77 txiout 78 txactive 79 n.c. 80 v ss 81 v dd 82 n.c. 83 rxactive 84 rxmsmpl 85 mfld 86 mncoen 87 rxmabrt 88 rxmdet 89 v ss 90 v dd 91 rxiin 0 92 rxiin 1 93 rxiin 2 94 rxiin 3 95 rxiin 4 96 rxiin 5 97 rxiin 6 98 rxiin 7 99 n.c. 100 v ss note: i.c. denotes internal connection. do not use for vias. .com .com .com .com 4 .com u datasheet
5 STEL-2000A general description the STEL-2000A is a programmable single-chip spread spectrum transceiver. the device performs all the digital processing required to implement a fast acquisition direct sequence (i.e., pseudonoise- or pn- modulated) spread spectrum full- or half-duplex sys- tem using differentially encoded bpsk, qpsk, or p /4 qpsk. a block diagram of the STEL-2000A is shown in figure 1, while the package style and pin configu- ration are shown in figure 2. the STEL-2000A is available in two speed grades; the STEL-2000A+20 (20 mhz maximum clock frequency), and the STEL-2000A+45 (45.056 mhz maximum clock fre- quency). the 45 mhz version features a high thermal conductivity package for superior heat dissipation, allowing the device to operate continuously at this speed. the STEL-2000A integrates the capabilities of a digital downconverter, pn matched filter, and dpsk demodulator into a single receiver, where the receiver input is the analog-to-digital converted i.f. signal. STEL-2000A transmit functions include a differential bpsk/qpsk encoder, pn modulator (spreader), and bpsk/qpsk modulator, where the transmitter output is a sampled digitally modulated signal ready for external digital-to-analog conversion (or, if preferred, the spread baseband signal may be output to an external modulator). these transceiver functions have been designed and integrated for the transmission and reception of bursts of spread data. in particular, the pn matched filter has two distinct pn coefficient registers (rather than a single one) in order to speed and improve signal acquisition performance. the STEL-2000A is thus optimized to provide reliable, high-speed wireless data communications. the STEL-2000A operates with symbol-synchronous pn modulation in both transmit and receive modes. symbol-synchronous pn modulation refers to opera- tion where the pn code is aligned with the symbol transitions and repeats once per symbol. by synchro- nizing a full pn code cycle over a symbol duration, acquisition of the pn code at the receiver simultane- ously provides symbol synchronization, thereby sig- nificantly improving overall acquisition time. the receiver clock rate ( rxifclk frequency) must be at least four times the receive pn spreading rate and is limited to a maximum speed of 45.056 mhz (STEL-2000A+45 only, 20 mhz in the stel- 2000a+20) . as a result, the maximum supported pn chip rate is 11.264 mchips/second (5 mcps in the STEL-2000A+20), where a chip is a single bit of the pn code. since pn modulation is symbol-syn- chronous in the STEL-2000A, the data rate is defined by the pn chip rate and length of the pn code; i.e., by the number of chips per symbol. when operating with bpsk modulation, the maximum data rate for a pn code of length n is 11.264/n mbps (stel- 2000a+45 only, 5/n mbps in the stel- 2000a+20) . when operating with qpsk modulation (or p /4 qpsk with an external modulator), two bits of data are transmitted per symbol, and the maximum data rate for a pn code of length n is 22.528/n mbps (STEL-2000A+45 only, 10/n mbps in the stel- 2000a+20) . conversely, for a given data rate rb, the length n of the pn code employed must be such that the product of n x rb is less than 11.264 (for bpsk) or 22.528 (for qpsk) mcps (STEL-2000A+45 only). the data rate (rb) and the pn code length (n), how- ever, cannot generally be arbitrarily chosen. united states fcc part 15.247 regulations require a minimum processing gain of 10 db for unlicensed operation in the industrial, scientific, and medical (ism) bands, implying that the value of n must be at least 10. to implement such a short code, a barker code of length 11 would typically be used in order to obtain desir- able auto- and cross-correlation properties. with the STEL-2000A, a pn code length of 11 implies that the maximum data rate supported by the STEL-2000A in compliance with fcc regulations is 2.048 mbps using differential qpsk (STEL-2000A+45 only). the stel- 2000a further includes transmit and receive code overlay generators to insure that signals spread with such a short pn code length possess the spectral properties required by fcc regulations. the STEL-2000A receiver circuitry employs an nco and complex multiplier referenced to rxifclk to perform frequency downconversion, where the input i.f. sampling rate and the clock rate of rxifclk must be identical. in complex input or quadrature sampling mode, external dual analog-to-digital con- verters (adcs) sample quadrature i.f. signals so that the STEL-2000A can perform true full single sideband downconversion directly from i.f. to baseband. at pn chip rates less than one-eighth the value of rxifclk , downconversion may also be effected using a single adc in real input or direct i.f. sampling mode, as discussed in appendix i. the input i.f. frequency is not limited by the capabili- ties of the STEL-2000A. to avoid destructive aliasing, the nco should not be programmed above 50% of the i.f. sampling rate (the frequency of rxifclk ); moreover, the signal bandwidth, nco frequency, and .com .com .com .com 4 .com u datasheet
STEL-2000A 6 i.f. sampling rate are all interrelated, as discussed in appendixi. higher i.f. frequencies, however, can be supported by programming the nco to operate on in-band aliases as generated by the sampling process. for example, a spread signal presented to the stel- 2000a?s receiver adcs at an i.f. frequency of f i.f. , where f rxifclk < f i.f. < 2 x f rxifclk , can generally, as allowed by the signal?s bandwidth, be supported by programming the STEL-2000A?s nco to a frequency of (f i.f. - f rxifclk ), as discussed in appendix i of this product specification. the maximum i.f. frequency is then limited by the track-and-hold capabilities of the adc(s) selected. signals at i.f. frequencies up to about 100 mhz can be processed by currently avail- able 8-bit adcs, but the implementation cost as well as the performance can typically be improved by using an i.f. frequency of 30 mhz or lower. down- conversion to baseband is then accomplished digitally by the STEL-2000A, with a programmable loop filter provided to establish a frequency tracking loop the STEL-2000A is designed to operate in either burst or continuous mode: in burst mode, built-in symbol counters allow bursts of up to 65,533 symbols to be automatically transmitted or received, while, in con- tinuous mode, the data is simply treated as a burst of infinite length. the STEL-2000A?s use of a digital pn matched filter for code detection and despreading permits signal and symbol timing acquisition in just one symbol. the fast acquisition properties of this design are exploited by preceding each data burst with a single acquisition/preamble symbol, allowing different pn codes (at the same pn chip rate) to inde- pendently spread the acquisition/preamble and data symbols. in this way, a long pn code with high pro- cessing gain can be used for the acquisi- tion/preamble symbol to maximize the probability of burst detection, and a shorter pn code can be used thereafter to permit a higher data rate. to improve performance in the presence of high noise and interference levels, the STEL-2000A receiver?s symbol timing recovery circuit incorporates a flywheel circuit to maximize the probability of cor- rect symbol timing. this circuit will insert a symbol clock pulse if the correlation peak obtained by the pn matched filter fails to exceed the programmed detect threshold at the expected time during a given symbol. during each burst, a missed detect counter tallies each such event to monitor performance and allow a burst to be aborted in the presence of abnormally high interference. a timing gate circuit further minimizes the probability of false correlation peak detection and consequent false symbol clock generation due to noise or interference. to minimize power consumption, individual sections of the device can be turned off when not in use. for example, the receiver circuitry can be turned off dur- ing transmission and, conversely, the transmitter cir- cuitry can be turned off during reception when the STEL-2000A is operating in a half-duplex/time divi- sion duplex (tdd) system. if the nco is not being used as the bpsk/qpsk modulator (i.e., if an external modulator is being used), the nco can also be turned off during transmission to conserve still more power. the fast acquisition characteristics of the STEL-2000A make it ideal for use in applications where bursts are transmitted relatively infrequently. in such cases, the device can be controlled so that it is in full sleep mode with all receiver, transmitter, and nco func- tions turned off over the majority of the burst cycle, thereby significantly reducing the aggregate power consumption. since the multiply operations of the pn matched filter consume a major part of the overall power required during receiver operation, two independent power-saving techniques are also built into the pn matched filter to reduce consumption during operation by a significant factor for both short and long pn spreading codes. the above features make the STEL-2000A an extremely versatile and useful device for spread spec- trum data communications. operating at its highest rates, the STEL-2000A is suitable for use in wireless local area network implementations, while its pro- grammability allows it to be used in a variety of data acquisition, telemetry, and transaction system applications. .com .com .com .com 4 .com u datasheet
7 STEL-2000A functional blocks transmit and receive clock generators timing in the transmitter and receiver sections of the STEL-2000A is controlled by the transmit and receive clock generator blocks. these blocks are programmable dividers providing signals at the chip and symbol rates (as well as at multiples and sub- multi ples of these frequencies) as programmed through the STEL-2000A?s control registers. if desired, the com plete independence of the transmitter and receiver sections allows the transmit and receive clocks to be mutually asynchronous. additionally, the STEL-2000A allows external signals to be provided as references for the transmit ( txmchp ) and receive ( rxmsmpl ) chip rates. given the transmit pn chip rate, the pn-synchronous transmit symbol rate is then derived from the programmed number of pn chips per transmit symbol. at the receiver, symbol synchronization and the receive symbol rate are determined from processing of the pn matched filter output, or, if desired, can be provided from the programmed number of pn chips per receive symbol or an external symbol sync symbol, rxmdet . burst control is achieved by means of the transmit and receive symbols per burst counters. these programmable 16-bit counters allow the STEL-2000A to operate automatically in burst mode, stopping at the end of each burst without the need of any external counters. input and output processors when the transmitter and receiver are operating in qpsk mode, the data to be transmitted and the received data are processed in pairs of bits (dibits), one bit for the in-phase (i) channel and one for the quadrature (q) channel. dibits are transmitted and received as single differentially encoded qpsk sym- bols. single-bit i/o data is converted to and from this format by the input and output processors, accepting txin as the serial data to be transmitted and produc- ing rxout as the serial data output. if desired, the received data is also available at the rxiout and rxqout pins in (i and q) dibit format prior to dibit- to-serial conversion. while receive timing is derived by the STEL-2000A symbol tracking processor, transmit timing is provided by the input processor. in bpsk mode, the input processor will generate the txbitpls signal once per symbol to request each bit of data, while in qpsk mode it will generate the txbitpls signal twice per symbol to request the two bits of data corresponding to each qpsk symbol. differential encoder data to be transmitted is differentially encoded before being spread by the transmit pn code. differential encoding of the signal is fundamental to operation of the STEL-2000A?s receiver: the STEL-2000A?s dpsk demodulator computes dot and cross product functions of the current and previous symbols? down- converted i and q signal components in order to per- form differential decoding as an intrinsic part of dpsk demodulation. the differential encoding scheme depends on whether the modulation format is to be bpsk or qpsk. for dbpsk, the encoding algorithm is straightforward: output bit(k) equals input bit(k) ? output bit(ke1), where ? represents the logical xor function. for dqpsk, however, the differential encoding algorithm, as shown in table 1, is more complex since there are now sixteen possible new states depending on the four possible previous output states and four possible new input states. new input previously encoded out(i, q) ke1 in(i, q) k 00 01 11 10 00 00 01 11 10 01 01 11 10 00 11 11 10 00 01 10 10 00 01 11 newly encoded out(i, q) k table 1. qpsk differential encoder sequence transmitter pn code generation when the STEL-2000A is used for burst signal opera- tion, each burst is preceded by an acquisi- tion/preamble symbol to facilitate acquisition. this acquisition/preamble symbol is automatically gener- ated by the STEL-2000A?s transmitter before informa- tion data symbols are accepted for transmission. two separate and independent pn codes may be employed: one for spreading the acquisi- tion/preamble symbol, and one for the subsequent information data symbols. as a result, a much higher processing gain may be used for signal acquisition than for signal tracking in order to improve burst acquisition performance. the transmitter acquisition/preamble and transmit- ter data symbol pn code lengths are completely independent of each other and can be up to 64 chips long. transmit pn codes are programmed in the STEL-2000A as binary code values. the number of transmitter chips per acquisition/preamble symbol is set by the value stored in bits 5-0 of address 43 h , and the transmitter acquisition/preamble symbol code coefficient values are stored in addresses 44 h to 4b h . the number of transmitter chips per data .com .com .com .com 4 .com u datasheet
STEL-2000A 8 symbol is set by the data stored in address 42 h , and the transmitter data symbol code coefficient values are stored in addresses 4c h to 53 h . a rising edge of the mtxen input or of bit 1 of address 37 h causes the STEL-2000A to begin the transmit sequence by transmitting a single symbol using the acquisition/preamble pn code. the com- pletion of transmission of the acquisition/preamble symbol is indicated with txacqpls , while the ongoing transmission of data symbols is signaled with txtrkpls . data bits to be transmitted after the acquisition/preamble symbol are requested with txbitpls , where a single pulse per symbol requests data in bpsk mode and two pulses per symbol request data in qpsk mode. the user data symbols are then pn modulated using the transmitter data symbol pn code. the pn spreading codes are xored with the data bits (in bpsk mode) or bit pairs (in qpsk mode) to transmit one complete code sequence for every acquisition/preamble and data symbol at all times. the resulting spread i and q channel signals are brought out as the txiout and txqout signals for use by an external modulator and are also fed into the STEL-2000A's internal modulator. in bpsk mode, only txiout is used by the STEL-2000A?s modula- tor. if an external qpsk modulator is used, the carrier should be modulated as shown in table 2 to be compatible with the STEL-2000A receiver. i, q bits signal quadrant quadrant diagram 0 0 first 1 0 second 2nd. 1st. 1 1 third 3rd. 4th. 0 1 fourth table 2. qpsk differential encoder sequence bpsk/qpsk modulator the STEL-2000A incorporates an on-chip bpsk/qpsk modulator which modulates the encoded and spread transmit signal with the sine and cosine outputs of the STEL-2000A?s nco to generate a digitized i.f. output signal, txifout 7-0 . since the nco operates at a rate defined by rxifclk , the bpsk/qpsk modulator output is also generated at this sampling rate, and, consequently, txifclk must be held common with rxifclk to operate the stel- 2000a?s bpsk/qpsk modulator. the digital modula tor output signal can then be fed into an external 8-bit dac (operating at rxifclk ) to generate an analog i.f. transmit signal, where the chosen i.f. is the STEL-2000A's programmed nco frequency or one of its aliases with respect to the output sampling rate, rxifclk . note that the maximum frequency of txifclk is specified at 20 mhz when the internal modulator is being used for both the 20 and 45 mhz versions of the STEL-2000A. for operation at higher frequencies than this an external bpsk or qpsk modulator should be used in conjunction with the txiout and txqout signals. when the STEL-2000A is set to transmit in bpsk mode (by setting bit0 of address 40 h high), identical signals are applied to both the i and q channels of the modulator so that the modulated output signal occu- pies only the first and third quadrants of the signal space defined in table 2. note that the modulator itself cannot generate p /4 qpsk signals, but the STEL-2000A can receive such signals and can be used with an external modulator for their transmission. frequency control register and nco the STEL-2000A incorporates a numerically con- trolled oscillator (nco) to synthesize a local oscilla- tor signal for both the transmitter's modulator and receiver's downconverter. the nco is clocked by the master receiver clock signal, rxifclk , and generates quadrature outputs with 32-bit frequency resolution. the nco frequency is controlled by the value stored in the 32-bit frequency control register, occupying 4 bytes at addresses 03 h to 06 h . to avoid destructive in-band aliasing, the nco should not be programmed to be greater than 50% of rxifclk . as desired by the user, the output of the STEL-2000A receiver?s loop filter can then be added or subtracted to adjust the nco's frequency control word and create a closed-loop frequency tracking loop. if the receiver is disabled, either manually or automatically at the end of a burst, the loop filter output correcting the nco?s frequency control word is disabled. when operating the transmitter and receiver simultane- ously, however, the receiver?s frequency tracking loop affects the nco signals to both the receive and transmit sides; this can either be used to advantage or must be compensated for in the system design. downconverter the STEL-2000A incorporates a quadrature (single sideband) downconverter which digitally downcon- verts the sampled and digitized receive i.f. signal to baseband. use of the loop filter and the nco's built- in frequency tracking loop permits the received signal to be accurately downconverted to baseband. the downconverter includes a complex multiplier in which the 8-bit receiver input signal is multiplied by the sine and cosine signals generated by the nco. in quadrature sampling mode, two adcs provide quadrature (complex) inputs i in and q in , while, in direct i.f. sampling mode, a single adc provides i in as a real input. the input signals can be accepted in .com .com .com .com 4 .com u datasheet
9 STEL-2000A either two?s complement or offset binary formats according to the setting of bit 3 of address 01 h . in direct i.f. sampling mode, the unused rxqin q channel input (q in ) should be held to zero accord- ing to the adc input format selected. the outputs of the downconverter?s complex multiplier are then: i out = i in . cos( w t) e q in . sin( w t) q out = i in . sin( w t) + q in . cos( w t) where w = 2 p f nco these outputs are fed into the i and q channel inte- grate and dump filters. the integrate and dump fil- ters allow the samples from the complex multiplier (at the i.f. sampling rate, the frequency of rxifclk ) to be integrated over a number of sample periods. the dump rate of these filters (the baseband sampling rate) can be controlled either by an internally gener- ated dump clock or by an external input signal ( rxmsmpl ) according to the setting of bit 0 of address 01 h . note that, while the receiver will extract exact pn and symbol timing information from the received signal, the baseband sampling rate must be twice the nominal pn chip rate for proper receiver operation and less than or equal to one-half the fre- quency of rxifclk . if twice the pn chip rate is a convenient integer sub-multiple of rxifclk, then an internal clock can be derived by frequency dividing rxifclk according to the divisor stored in bits 5-0 of address 02 h ; otherwise, an external baseband sam- pling clock provided by rxmsmpl must be used. the i.f. sampling rate, the baseband sampling rate, and the input signal levels determine the magnitudes of the integrate and dump filters? accumulator out- puts, and a programmable viewport is provided at the outputs of the integrate and dump filters to select the appropriate output bits as the 3-bit inputs to the pn matched filter. the viewport circuitry here and elsewhere within the STEL-2000A?s receiver is designed with saturation protection so that extreme values above or below the selected range are limited to the correct maximum or minimum value for the selected viewport range. the viewports for the i and q channels of the integrate and dump filters are con- trolled by the values stored in bits 7-4 of address 01 h . receiver pn code register and pn matched filter thr eshold registers aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa i delay register block aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa q dela y register block coefficient memory and register block i multiplier a rra y block q multiplier a rra y block i adder q a dder aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa aaaaaaaaaaaaa post processor block in i in q aaaaa aaaaa s s abs abs magnitude genera tor comp- arator su m i su m q mag de t ta p1 ta p2 ta p0 ta p63 ta p64 2t 2t 2t 2t 2t 2t 2t 2t 2t 2t ta p62 aaaa 8 8 8 aa aa aa + + + + + + + + + + + + + + fep block 3 t 3 t v iewport and sat. (output control) 10 10 10 a qu.-pre./da ta coef. sel. m p se l m d m p se l m d m p se l m d se l m p se l m d m p se l m d aaaa aaaa aaaa fep block aaaa aaaa aaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa figure 3. matched filter detail as discussed for the STEL-2000A transmitter, the STEL-2000A is designed for burst signal operation in which each burst begins with a single acquisi- tion/preamble symbol and is then followed by data symbols for information transmittal. complementing operation of the STEL-2000A?s transmitter, two sepa- rate and independent pn codes may be employed in the receiver?s pn matched filter, one for despreading .com .com .com .com 4 .com u datasheet
STEL-2000A 10 the acquisition/preamble symbol, and one for the information data symbols. the code lengths are completely independent of each other and can be each up to 64 chips long. a block diagram of the pn matched filter is shown in figure 3. the STEL-2000A contains a fully programmable 64- tap complex (i.e., i and q channel) pn matched filter with coefficients which can be set to 1 or zero according to the contents of either the acquisi- tion/preamble or data symbol code coefficient reg- isters. by setting the coefficients of the end taps of the filter to zero, the effective length of the filter can be reduced for use with pn codes shorter than 64 bits. power consumption may also be reduced by turning off those blocks of 7 taps for which all the coefficients are zero, using bits 6-0 of address 39 h . each ternary coefficient is stored as a 2-bit number, so that a pn code of length n is stored as n 2-bit non-zero pn coefficients. note that, as a convention, throughout this document the first pn matched filter tap encoun- tered by the signal as it enters the i and q channel tapped delay lines is referred to as tap 0. tap 63 is then the last tap of the pn matched filter. the start of each burst is expected to be a single sym- bol pn-spread by the acquisition/preamble code. the receiver section of the STEL-2000A is automati- cally configured into acquisition mode so that the matched filter acquisition/preamble coefficients stored in addresses 07 h to 16 h are used to despread the received signal. provided that this symbol is suc- cessfully detected, the receiver will automatically switch from acquisition mode, and the matched filter data symbol coefficients stored in addresses 17 h to 26 h will then be used to despread subsequent symbols. to allow the system to sample the incoming signal asyn chronously (at the i.f. sampling rate) with respect to the pn spreading rate, the pn matched fil- ter is designed to operate with two signal samples (at the baseband sampling rate) per chip. a front end processor (fep) operating on both the i and q chan- nels averages the incoming data over each chip period by adding each incoming baseband sample to the previous one: i.e., fep out = fep in (1 + z e1 ) after the addition, the output of the fep is rounded to a 3-bit offset 2?s complement word with an effective range of 3.5. such that the rounding process does not introduce any bias to the data. the fep can be disabled by setting bit 0 of address 27 h to a 1, but for normal operation the fep should be enabled. the pn matched filter computes the cross-correlation between the i and q channel signals and the locally stored pn code coefficients at the baseband sampling rate; i.e., twice per chip. the 3-bit signals from each tap in the pn matched filter are multiplied by the corresponding coefficient in two parallel tapped delay lines. each delay line consists of 64 multipliers which multiply the delayed 3-bit signals by zero or 1 according to the value of the tap coefficient. the products from the i and q tapped delay lines are added together in the i and q adders to form the sums of the products, representing the complex cross- correlation factor. the correlation i and q outputs are thus: n = 63 output (i, q) = s data n(i, q) * coefficient n(i, q) n = 0 these i and q channel pn matched filter outputs are 10-bit signals, with i and q channel programmable viewports provided to select the appropriate output bits as the 8-bit inputs to the power detector and dpsk demodulator blocks. both i and q channel viewports are jointly controlled by the data stored in bits 1-0 of address 28 h and are saturation protected. two power saving methods are used in the pn matched filter of the STEL-2000A. as discussed pre- viously, the first method allows power to be shut off in the unused taps of the pn matched filter when the filter length is configured to be less than 64 taps. the second method is a proprietary technique that (transparently to the user) shuts down the entire pn matched filter during portions of each symbol period. power detector the complex output of the pn matched filter is fed into a power detector which, for every cycle of the internal baseband sampling clock, computes the mag- nitude of the vector of the i and q channel correlation sums, i 2 (k)+q 2 (k) , where the magnitude is approx- imated as max{abs(i),abs(q)} + 1/ 2 min{abs(i), abs(q)}. this 10-bit value represents the power level of the correlated signal during each chip period and is used in the symbol tracking processor. symbol tracking processor the output of the power detector block represents the signal power during each chip period. ideally, this output will have a high peak value once per symbol (i.e., once per pn code cycle) when the code sequence of the received signal in the pn matched filter is the same as (and is aligned in time with) the reference pn code used in the pn matched filter. at that instant, the i and q channel outputs of the pn matched filter .com .com .com .com 4 .com u datasheet
11 STEL-2000A are, theoretically, the optimally despread i and q symbols. to detect this maximum correlation in each symbol period, the signal power value is compared against a 10-bit user-programmable threshold value. a symbol clock pulse is generated each time the power value exceeds the threshold value to indicate a symbol detect. since the acquisition/preamble symbol and subsequent data symbols can have different pn codes with different peak correlation values (which depend on the pn code length and code properties), the STEL-2000A is equipped with two separate threshold registers to store the acquisition/preamble threshold value (stored in addresses 29 h and 2a h ) and the data symbol threshold value (stored in addresses 2b h and 2c h ). the device will automatically use the appro- priate value depending on whether it is in acquisition mode or not. since spread spectrum receivers are frequently designed to operate under extremely adverse signal- to-noise ratio conditions, the STEL-2000A is equipped with a flywheel circuit to enhance the operation of the symbol tracking function by introducing memory to the pn matched filter operation. this circuit is designed to ignore false detects at inappropriate times in each symbol period and to insert a symbol clock pulse at the appropriate time if the symbol detection is missed. the flywheel circuit operates by its a priori knowledge of when the next detect pulse is expected. the expected pulse will occur one symbol period after the last correctly detected one, and a window of 1 baseband sample time is therefore used to gate the detect pulse. any detects generated outside this time window are ignored, while a symbol detect pulse will be inserted into the symbol clock stream if the power level does not exceed the threshold within the win- dow, corresponding to a missed detect. an inserted symbol detect signal will be generated precisely one symbol after the last valid detect, the nominal symbol length being determined by the value of rx chips per data symbol stored in address 2d h . the cross-correlation characteristics of a noisy received signal with the noise-free local pn code used in the STEL-2000A?s pn matched filter may result in smearing of the peak power value over adjacent chip periods. such smearing can result in two or three consecutive power values (typically, the on-time and one-sample early and late values) exceeding the threshold. a maximum power selector circuit is incorporated in the STEL-2000A to choose the highest of any three consecutive power levels each time this occurs, thereby enhancing the probability that the optimum symbol timing will be chosen in such cases. if desired, this function can be disabled by setting bit 3 of address 30 h high. the STEL-2000A also includes a circuit to keep track of missed detects; i.e., those cases where no peak power level exceeds the set threshold. an excessively high rate of missed detects is an indication of poor signal quality and can be used to abort the reception of a burst of data. the number of symbols expected in each receive burst, up to a maximum of 65,533, is stored in addresses 2e h and 30 h . a counter is used to count the number of missed detects in each burst, and the system can be configured to automatically abort a burst and return to acquisition mode if this number exceeds the missed detects per burst threshold value stored in address 2f h . under normal operating con- ditions, the STEL-2000A will automatically return to acquisition mode when the number of symbols pro- cessed in the burst is equal to the value of the data stored in address 2e h and 30 h . to permit the pro- cessing of longer bursts or continuous data, this func- tion can be disabled by setting bit 6 of address 30 h high. differential demodulator both dpsk demodulation and carrier discrimination are supported in the STEL-2000A receiver by the cal- culation of dot and cross products using the despread i and q channel information generated by the pn matched filter for the current and previous symbols. a block diagram of the dpsk demodula- tor?s i and q channel processing is shown in figure 4. let i k and q k represent the i and q channel outputs, respectively, for the k th symbol. the dot and cross products can then be defined as: dot(k) = i k i k-1 + q k q k-1 ; and, cross(k) = q k i k-1 - i k q k-1 . examination of these products in the complex plane reveals that the dot and cross products are the real and imaginary results, respectively, of complex mul- tiplication of the current and previous symbols. the dot product alone thus allows determination of the phase shift between successive bpsk symbols, while the dot and cross products together allow .com .com .com .com 4 .com u datasheet
STEL-2000A 12 t dela y i k ?1 + 1 + j x x = 0, +1, -1 = 0, +45, -45 + + 17 cross(k) = q k . i k ?1 ?i k . q k ?1 17 dot(k) = i k . i k 1 + q k . q k ?1 8 8 i q symbol rota tor q k 1 i k q k s s figure 4. differential demodulator detail determination of the integer number of p /2 phase shifts between successive qpsk symbols. differential encoding of the source data implies that an absolute phase reference is not required, and thus knowledge of the phase shift between successive symbols derived from the dot and cross products unambiguously permits correct demodulation. implementation of this approach is simplified if the polarities (i.e., the signs) alone of the dot and cross products provide the information required to make the correct symbol decision. for bpsk and p /4 qpsk signals, no modifications are needed: in bpsk, the sign of the dot product fully captures the signal con- stellation, while, in p /4 qpsk, the signal constellation intrinsically includes the phase rotation needed to align the decision boundaries with the four possible combinations of the dot and cross product polarities. for qpsk signals, a fixed phase rotation of p /4 (45 ) is introduced in the dpsk demodulator to the previ- ous symbol to simplify the decision algorithm. rota- tion of the previous symbol is controlled by the set- tings of bits 0 and 1 of address 33 h ,allowing the pre- vious symbol to be rotated by 0 or 45 . as noted, for bpsk or p /4 qpsk signals, a rotation of 0 should be programmed, but, for qpsk signals, a e45 signal rotation must be programmed to optimize the constel- lation boundaries in the comparison process between successive symbols. note also that introduction of a 45 rotation introduces a scaling factor of 1 / ? 2 to the signal level in the system as discussed in appendix i, where this factor should be taken into account when calculating optimum signal levels and viewport set- tings after the dpsk demodulator. frequency discriminator and loop filter + qpsk bpsk mux bpsk/ qpsk select 17 cross dot sign sign 31 view - port afc view port control 4 29 32 k1 k2 ? to nco 29 8 a inv . lf reg. frz. lf fc w s s s s figure 5. frequency discriminator and loop filter detail .com .com .com .com 4 .com u datasheet
13 STEL-2000A the frequency discriminator uses the dot and cross products discussed above to generate the afc signal for the frequency acquisition and tracking loop, as illustrated in figure 5. the specific algorithm used depends on the signal modulation type and is con- trolled by the setting of bit 2 of address 33 h . when bit 2 is set low, the frequency discriminator circuit is in bpsk mode and the following algorithm is used to compute the frequency discriminator (fd) function: fd = cross x sign[dot], where sign[dot] represents the polarity of the argu- ment. when bit 2 is set high, the discriminator cir- cuitry is in qpsk mode and the carrier discriminator function is instead calculated as: fd = (cross x sign[dot]) e (dot x sign[cross]). in both cases, the frequency discriminator function provides an error signal that reflects the change in phase between successive symbols. with the symbol period known, the error signal can equivalently be seen as a frequency error signal. as a practical mat- ter, the computation of the frequency discriminator function results in a 17-bit signal, and a pro- grammable saturation protected viewport is provided to select the desired output bits as the 8-bit input to the loop filter block. the viewport is controlled by the value stored in bits 7-4 of address 33 h . the loop filter is implemented with a direct gain (k1) path and an integrated or accumulated (k2) path to filter the frequency discriminator error signal and correct the frequency tracking of the downconverter. the order of the loop filter transfer function can be set by enabling or disabling the k1 and k2 paths, and the coefficient values can be adjusted in powers of 2 from 2 0 to 2 21 . the loop filter transfer function is: transfer fn. = k1 + 1 / 4 k2 z e1 1ez e1 the factor of 1 / 4 results from truncation of the 2 lsbs of the signal in the integrator path of the loop so that, when added to the signal in the direct path, the lsbs of the signals are aligned. the coefficients k1 and k2 are defined by the data stored in bits 4-0 of addresses 35 h and 34 h , respectively. in addition, bit 5 of addresses 35 h and 34 h control whether the k1 and k2 paths, respectively, are enabled. these parameters thus give the user full control of the loop filter characteristics. .com .com .com .com 4 .com u datasheet
STEL-2000A 14 input signals rxiin 7-0 (pins 91-98) receiver in-phase input. rxiin is an 8-bit input port for in-phase data from external a/d converters. data may be received in either two's complement or offset binary format as selected by bit 3 of address 01 h . the sampling rate of the rxiin signals (the i.f. sampling rate of the a/ds) may be independent of the base- band sampling rate (the downconverter integrate and dump rate) and the pn chip rate, but must be equal to rxifclk and at least two times greater than the baseband sampling rate. since the baseband sam- pling rate must be set at twice the pn chip rate, the i.f. sampling rate must thus be at least four times the pn chip rate. data on the pins is latched and pro- cessed by rxifclk . rxqin 7-0 (pins 2-9) receiver quadrature-phase input. rxqin is an 8- bit input port for quadrature-phase data from external a/d converters. data may be received in either two's complement or offset binary format as selected by bit 3 of address 01 h . as with rxiin , the sampling rate of the rxqin signals may be independent of the baseband sampling and pn chip rates in the receiver, but must be at least two times greater than the baseband sample rate (or, equiva- lently, at least four times greater than the pn chip rate). data on the pins is latched and processed by rxifclk . note that if the STEL-2000A is to be used in direct i.f. sampling mode, then the i.f. signal should be input to the rxiin input port only. rxqin must then be held to arithmetic zero according to the chosen adc format as selected by bit 3 of address 01 h . in other words, to support direct i.f. sampling, rxqin must be tied to a value of 7f h or 80 h if offset binary input format has been selected or to a value of 00 h if two?s complement input format has been selected. rxmsmpl (pin 84) receiver manual sample clock. rxmsmpl enables the user to externally generate (independent of the i.f. sampling clock, rxifclk ) the baseband sampling clock used for all processing after the digital down- converter, including the dump rate of the integrate and dump filters. this feature is useful in cases where a specific baseband sample rate is required that may not be derived by the internal sample rate timing genera tor which generates clock signals at integer sub-multiples of rxifclk . the signal is internally synchro nized to rxifclk to avoid intrinsic race or hazard timing conditions. there must be at least two cycles of rxifclk to every cycle of rxmsmpl , and rxmsmpl should be set to twice the nominal receive pn chip rate. when bit 0 of address 01 h is set high, a rising edge on rxmsmpl will initiate a baseband sampling clock pulse to the integrate and dump filters and subse- quent circuitry (e.g., pn matched filter, dpsk demodulator, power estimator, etc.). the rising edge of rxmsmpl is synchronized internally so that, on the second rising edge of rxifclk that follows the rising edge of rxmsmpl , a pulse is internally gener- ated that clocks the circuitry that follows. on the third rising rxifclk edge, the contents of the inte- grate and dump filters of the downconverter are transferred to the pn matched filter. the extra one rxifclk delay before transfer of the contents of the filters enables the internally generated baseband sam- pling clock to be free of race conditions at the inter- face between the downconverter and pn matched filter. rxmdet (pin 88) receiver manual detect. rxmdet enables the user to externally generate symbol timing, bypassing and overriding the internal symbol power estimation and tracking circuitry. this function may be useful when the dynamic characteristics of the transmission envi- ronment require unusual adjustments to the symbol timing. when bit 0 of address 30 h is set high (manual detect enable) and when bit 0 of address 31 h is set low, a rising edge of rxmdet will generate a symbol corre- lation detect pulse. the function can also be per- formed by means of bit 0 of address 31 h. the rxmdet input and bit 0 of address 31 h are logically ored together so that, when either one is held low, a rising edge on the other triggers the manual detect function. the rising edge of rxmdet is synchro- nized internally so that, on the second rising edge of the baseband sampling clock that follows the rising edge of rxmdet , the correlated outputs of the pn matched filter i and q channels will be transferred to the dpsk demodulator. rxmabrt (pin 87) receiver manual abort. rxmabrt enables the user to manually force the STEL-2000A to cease reception of the current burst of data symbols and prepare for acquisition of a new burst. this function can be used to reset the receiver and prepare to receive a priority transmission signal under precise timing control, giv- ing the user the ability to control the status of the receiver for reasons of priority, signal integrity, etc. when bit 0 of address 32 h is set low, a rising edge on .com .com .com .com 4 .com u datasheet
15 STEL-2000A rxmabrt will execute the abort function. the function can also be performed under microprocessor control by means of bit 0 of address 32 h. the rxmabrt input and bit 0 of address 32 h are logi- cally ored together so that, when either one is held low, a rising edge on the other triggers the abort func- tion. the second rising edge of the baseband sam- pling clock that follows a rising edge of rxmabrt will execute the abort and also clear the symbols-per- burst, samples-per-symbol, and missed-detects-per- burst counters. the counters will be reactivated on the detection of the next burst preamble or by a man- ual detect signal. rxifclk (pin 12) receiver i.f. clock. rxifclk is the master clock of the nco and all the receiver blocks. all clocks in the receiver section and the nco, internal or external, are generated or synchronized internally to the rising edge of rxifclk . the frequency of rxifclk must be at least four times the pn chip rate of the received signal. when bit 0 of address 01 h is set low, the base- band sampling clock, required to be at twice the nom- inal pn chip rate, will be derived from rxifclk according to the setting of bits 5-0 of address02 h . mncoen (pin 86) manual nco enable. mncoen allows the power consumed by the operation of the nco circuitry to be minimized when the STEL-2000A is not receiving and not transmitting data. the nco can also be disabled while the STEL-2000A is transmitting as long as the STEL-2000A's on-chip bpsk/qpsk modulator is not being used. with the instantaneous acquisition prop- erties of the pn matched filter, it is often desirable to shut down the receiver circuitry to reduce power con- sumption, resuming reception periodically until an acquisition/preamble symbol is acquired. setting mncoen low will do this by holding the nco in a reset state. after mncoen has been set high again to re-activate the nco it will be necessary to reload the frequency control word into the nco. note that mncoen operates independently of mtxen and mrxen, where those pins have similar control over the transmit and receive circuitry, respectively. mncoen performs the same function as bit 0 of address 37 h , and these two signals are logically ored together to form the overall control function. when this bit is set low, mncoen controls the activity of the nco circuitry; when mncoen is set low, bit 0 of address 37 h controls the activity of the nco circuitry. when either bit 0 or mncoen (whichever is in con- trol, as defined above) goes low, a reset sequence occurs on the following rxifclk cycle to effectively disable all of the nco circuitry, although the user programmable control registers are not affected by this power down sequence. upon reactivation (when either mncoen or bit 0 of address 37 h return high), the nco must be reloaded with frequency control information either by means of the mfld input or by writing 01 h into address 00 h . mtxen (pin 17) manual transmitter enable. a rising edge on mtxen causes the transmit sequence to begin, where the STEL-2000A first transmits a single acquisi- tion/preamble symbol followed by data symbols. mtxen should be set low after the last symbol has been transmitted. when mtxen is set low, power consumption of the transmitter circuit is minimized. mtxen operates independently of mrxen and mncoen, where these signals have similar control over the receive and nco circuitry, respectively. mtxen performs the same function as bit 1 of address 37 h . and these two signals are logically ored together to form the overall control function. when bit 1 of address 37 h is set low, mtxen controls the activity of the transmitter circuitry, and, when mtxen is set low, bit 1 of address 37 h controls the activity of the transmitter circuitry. a rising edge on either mtxen or bit 1 (whichever is in control, as defined above) initiates a transmit sequence. a falling edge initiates a reset sequence on the following txifclk cycle to disable all of the transmitter data path, although the user programmable control regis- ters are not affected by the power down sequence. mrxen (pin 10) manual receiver enable. mrxen allows power consumption of the STEL-2000A receiver circuitry to be minimized when the device is not receiving. with the instantaneous acquisition properties of the pn matched filter, it is often desirable to shut down the receiver circuitry to reduce power consumption, resuming reception periodically until an acquisi- tion/preamble symbol is acquired. setting mrxen low reduces the power consumption substantially. when mrxen is set high, the receiver will automati- cally power up in acquisition mode regardless of its prior state when it was powered down. mrxen operates independently of mtxen and mncoen , where these signals have similar control over the transmit and nco circuitry, respectively. mrxen performs the same function as bit 2 of address 37 h , and these two signals are logically ored together to form the overall control function. when bit 2 of address 37 h is set low, mrxen controls the activity of the receiver circuitry and, when mrxen is set low, bit 2 of address 37 h controls the activity of the receiver circuitry. when either mrxen or bit 2 (whichever is in control, as defined above) goes low, a reset sequence begins on the following rxifclk .com .com .com .com 4 .com u datasheet
STEL-2000A 16 cycle and continues through a total of six rxifclk cycles to virtually disable all of the receiver data paths, although the user programmable control regis- ters are not affected by the power down sequence. note that this reset sequence will also reset the con- tents of address 38 h to 0. if the rxtest 7-0 bus is being used for reading any function except the matched filter i and q inputs the value required must be re-written after re-enabling the receiver. txin (pin 18) transmit input. txin supports input of the informa- tion data to be transmitted by the STEL-2000A. in bpsk mode, the transmitter requires one bit per sym- bol period; in qpsk mode, two bits are required per symbol period. to initiate and enable transmission of the data, the user must raise mtxen high. data for transmission is requested with txbitpls , where one or two pulses per symbol are generated depending on whether the device is in bpsk or qpsk mode as set by bit 0 of address 40 h . to allow monitoring of the state of the transmitter, the STEL-2000A will pulse txacqpls after the initial acquisition/preamble symbol is transmitted; the transmission of each sub- sequent symbol is indicated by pulses of txtrkpls . if programmed for bpsk mode, data is requested by the STEL-2000A by a rising edge of output signal txbitpls , where txbitpls is generated once per symbol, one chip period before the end of the current symbol. at the end of the symbol duration, the txin data is latched into the device. txbitpls falls low immediately following the rising edge of txifclk , which latches the txin value, and is generated repeatedly at the symbol rate as long as the input sig- nal mtxen remains high. in qpsk mode, data is requested by the STEL-2000A by a rising edge of output signal txbitpls , where this signal is generated twice per symbol, first one chip period before the middle of the symbol and then one chip period before the end of the symbol. txbitpls requests the data exactly one chip cycle before latching the txin data into the device. txbitpls falls low immediately following the rising edge of txifclk , which latches the txin value. txmchp (pin 19) transmit manual chip pulse. txmchp enables the user to provide the pn chip rate clock pulses from an external source. this feature is useful in cases where a specific chip rate is required that cannot be derived by the internal clock generator which generates clocks of integer sub-multiples of txifclk . the signal is internally synchronized to txifclk to avoid intrin- sic race or hazard timing conditions. when bit 2 of address 40 h is set high, a rising edge on txmchp will generate the chip clock to the differen- tial encoder and the following circuitry (acquisition/preamble and data symbol pn spread- ers, etc.). the rising edge of txmchp is synchro- nized internally so that, on the third rising edge of txifclk following the rising edge of txmchp , the pn code combined with the differen tially encoded signal will change, generating the next chip. txifclk (pin 14) transmitter i.f. clock. txifclk is the master clock of the transmitter. all transmitter clocks, internal or external, are generated or synchronized internally to the rising edge of txifclk . the rate of txifclk must be at least twice the transmit pn chip rate. it may be convenient to use the same external signal for both txifclk and rxifclk , in which case the fre- quency of txifclk will be at least four times the pn chip rate as required for rxifclk . moreover, if the STEL-2000A's on-chip bpsk/qpsk modulator is to be used, txifclk and rxifclk must be identical and their frequencies must not exceed 20 mhz mfld (pin 85) manual frequency load. mfld is used to load a frequency control value into the nco. the nco may be loaded in various ways, but mfld provides a syn- chronized external method of updating the nco, while the other methods involve setting bit 0 of address 00 h or using the programmable loop filter timing circuitry. mfld is internally synchronized to rxifclk to avoid internal race or hazard timing conditions. the mfld input and bit 0 of address 00 h are logically ored together so that, when either one is held low, a rising edge on the other triggers the frequency load function manually. the rising edge of mfld is synchronized internally so that, on the sixth following rising edge of rxifclk , the frequency control word is completely registered into the nco accumulator. the frequency load command must not be repeated until the six rxifclk cycle delay is completed. wr (pin 28) write bar. wr eee is used to latch user-configurable information into the control registers. it is important to note that the control registers are transparent latches while wr eee is set low. the information will be latched when wr eee returns high. data 7-0 and addr 6-0 should be stable while wr eee is set low in order to avoid undesirable effects. data 7-0 (pins 20-27) data bus. data 7-0 is an 8-bit microprocessor inter- face bus that provides access to all internal control .com .com .com .com 4 .com u datasheet
17 STEL-2000A register inputs for programming. data 7-0 is used in conjunction with the addr 6-0 and wr eee signals to set the values of the control registers. addr 6-0 (pins 32-38) address bus. addr 6-0 is a 7-bit address bus that selects the control register location into which the information provided on the data 7-0 bus will be written. addr 6-0 is used in conjunction with wr eee and data 7-0 to write the information into the registers. csel (pin 29) chip select bar. csel eeeee is provided to enable or dis- able the microprocessor operation of the STEL-2000A. when csel eeeee is set high, the addr 6-0 and wr eee become disabled and have no effect on the device. when csel eeeee is set low, the device is in its normal mode of operation and addr 6-0 and wr eee are active. oen (pin 49) output enable bar. oen eeeee is provided to enable or disable the rxtest 7-0 output bus. when oen eeeee is set high, the rxtest 7-0 bus will have a high impedance, allowing it to be connected to other busses, such as data 7-0 . when oen eeeee is set low, the rxtest 7-0 bus will be active, allowing the rxtest function selected to be accessed. reset (pin 16) reset bar. reset eeeeee is the master reset of the stel- 2000a, clearing the control registers as well as the contents within the receiver, transmitter, and nco data paths when it is set low. setting reset eeeeee high enables operation of the circuitry. .com .com .com .com 4 .com u datasheet
STEL-2000A 18 output signals txiout (pin 77) transmitter in-phase output. txiout is the in- phase output transmission signal that has been differ- entially encoded and pn spread. txiout changes on the rising edge of txifclk following the falling edge of txchppls . txqout (pin 76) transmitter quadrature-phase output. txqout is the quadrature-phase output transmission signal that has been differentially encoded and pn spread. txqout changes on the rising edge of txifclk fol- lowing the falling edge of txchppls . txifout 7-0 (pins 66-73) txifout 7-0 is the modulated transmit output signal from the on-chip bpsk/qpsk modulator. the signal is composed of the sum of the modulated txiout and txqout signals, modulated by the nco cosine and sine outputs, respectively. since the modulator is driven by the STEL-2000A?s nco, txifout 7-0 changes on the rising edges of rxifclk , and opera- tion of the bpsk/qpsk modulator requires that rxifclk and txifclk be identical and their frequencies must not exceed 20 mhz txifout 7-0 may be in either two's complement or offset binary format according to the setting of bit 1 of address 40 h . txacqpls (pin 60) transmitter acquisition pulse. txacqpls is an output signal generated at the final chip of the acquisi tion/preamble symbol. the acquisit- ion/preamble symbol is generated automatically by the STEL-2000A upon user command (either via bit 1 of address 37 h or mtxen input) and immediately precedes transmission of user data. txacqpls is then provided to the user to indicate when the final chip of the acquisition/preamble symbol is being transmitted. txbitpls (pin 63) transmitter bit pulse. txbitpls is an output signal used to support transmission timing of user data for either bpsk or qpsk modes, as programmed by bit 0 of 40 h . in bpsk mode, user-provided data is requested by the STEL-2000A by a rising edge of txbitpls once per symbol . txbitpls requests the data one chip period before the txin data is latched into the device, and txbitpls falls low immediately following the rising edge of txifclk , where txifclk latches the txin value. in qpsk mode, user-provided data is requested by the STEL-2000A by a rising edge of output signal txbitpls which occurs twice per symbol, first one chip period before the middle of the symbol and then one chip period before the end of the symbol. txbitpls requests the data exactly one chip cycle period before the txin data is latched into the device. txbitpls falls low immediately following the rising edge of txifclk , where txifclk latches the txin value. in both modes the data must be valid on the second rising edge of txifclk after the rising edge of txbitpls . txchppls (pin 62) transmitter chip pulse. txchppls is an output signal used to support transmission timing for the device. txchppls pulses high for one txifclk cycle at the pn chip rate defined by the user. the chip rate is set either by programming a value in bits 5-0 of address 41 h or through use of the external txmchp signal. txtrkpls (pin 61) transmitter data track pulse. txtrkpls is an output signal that allows monitoring of data symbol transmissions. a rising edge of output signal txtrkpls occurs one chip period before the end of the current data symbol transmission. txtrkpls then falls low immediately following the rising edge of txifclk . txactive (pin 78) transmitter active. a high level on txactive indi- cates that the transmitter is sending data symbols. this signal will be set high at the end of the acquisi- tion/preamble symbol, indicating the start of the first chip of the first data symbol at the txiout and txqout pins. it will be set low at the end of the last chip period of the last data symbol of the burst at the txiout and txqout pins. rxout (pin 57) receiver output. rxout is the output data of the receiver following downconversion, despreading and demodulation. in bpsk mode, one data bit is pro- vided per symbol; in qpsk mode, two data bits are provided per symbol with a half-symbol separation between the bits. note that the data will be invalid during the first symbol of each burst ; i.e., in bpsk mode the first bit will be invalid and in qpsk mode the first two bits will be invalid. rxiout (pin 56) receiver i channel output . rxiout is the i channel output data before dibit-to-serial conversion. rxiout can be used in conjunction with the rxqout signal in applications where the qpsk out- .com .com .com .com 4 .com u datasheet
19 STEL-2000A put data is required as parallel bit pairs. note that the first bit of rxiout in each burst will be invalid. rxqout (pin 55) receiver q channel output. rxqout is the q channel output data before dibit-to-serial conversion. rxqout can be used in conjunction with the rxiout signal in applications where the qpsk data is required as parallel bit pairs. note that the first bit of rxqout in each burst will be invalid. rxdrdy (pin 54) receiver data ready bar. rxdrdy eeeeeeeee is provided as a receiver timing signal. rxdrdy eeeeeeeee is normally set high and pulses low during the baseband sampling clock cycle when a new rxout signal is generated. rxsplpls (pin 53) receiver sample pulse. rxsplpls is an output tim- ing signal that provides internal timing information to the user. rxsplpls is the internally generated base- band sampling clock, referenced either externally or internally according to the setting of bit 0 of address 01 h . all receiver functions, excluding those in the downconverter, trigger internally on the rising edge of rxsplpls . rxsympls (pin 52) receiver symbol pulse. rxsympls is an output signal that provides the user internal timing informa- tion relative to the detection/correlation of symbols. symbol information from the pn matched filter, dpsk demodulator, and output processor is trans- ferred on the rising edge of rxsplpls preceding the falling edge of rxsympls . rxactive (pin 83) receiver active. a high level on rxactive indi- cates that the receiver has detected an acquisi- tion/preamble symbol and is currently receiving data symbols. rxactive will be set high one bit period before the first rising edge of rxdrdy eeeeeeeee , indicating that the first data bit is about to appear at the rxout , rxiout , and rxqout pins. rxactive will be set low immediately following the last rising edge of rxdrdy eeeeeeeee , indicating that the last data bit of the burst has been output at the rxout , rxiout , and rxqout pins. rxtest 7-0 (pins 41-48) these pins provide access to 16 test points within the receiver as shown in figure 6. the pin outputs are selected according to the value in bits 3-0 of address 38 h and the assignments shown in table 3. when one of these 4-bit values is written into address 38 h , the corresponding function becomes available at the rxtest 7-0 outputs. note that the matched filter power output values, available when the value in bits 3-0 of address 38 h is set to either 1 h or 8 h , is an unsigned binary number, ranging from 0 to 255 (0 h to ff h ). all other signal values available at this port are in two?s complement, ranging from e128 to +127 (80 h to 7f h ). the rxtest 7-0 bus is a 3-state bus and is controlled by the oen input. note that the validity of the rxtest 7-0 bus signals at rxifclk frequencies over 20 mhz is dependent on the function selected. functions that change more rapidly than once per symbol may be indeterminate at clock frequencies higher than 20 mhz. note that the reset sequence that occurs whenever the receiver is disabled will also reset the contents of address 38 h to 0. if the rxtest 7-0 bus is being used for reading any function except the matched filter i and q inputs the value required must be re-written after disabling the receiver. txtest (pin 59) transmitter test output . txtest provides access to 3 test points within the transmitter as shown in figure 6. the pin output is selected according to the state of the two least significant bits of the address line, addr 1-0 and the assignments shown in table 4. note that this method of accessing the transmitter test points is completely different than the method by which the receiver test points are accessed. the state of the other address lines does not affect this function, and this function is always enabled. addr 1-0 txtest description 0 h isym unspread i symbol 1 h qsym unspread q symbol 2 h scode spreading code table 4. transmitter test functions note that the validity of the txtest bus signals at txifclk frequencies over 20 mhz is dependent on the function selected. functions that change more rapidly than once per symbol may be indeterminate at clock frequencies higher than 20 mhz. .com .com .com .com 4 .com u datasheet
STEL-2000A 20 bits 3-0 of 38 h rxtest 7-0 output bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 h mfqin 2-0 matched filter q input mfiin 2-0 matched filter i input 1 h pk-power 9-2 . mf peak magnitude output, unsigned binary (changes once per symbol) 2 h cos 7-0 . cosine output of nco (changes every cycle of rxifclk ) 3 h sin 7-0 . sine output of nco (changes every cycle of rxifclk ) 4 h dciout 16-9 . downconverter i channel output (changes at rxifclk rate) 5 h dcqout 16-9 . downconverter q output (changes at rxifclk rate) 6 h isum 9-2 . matched filter i output (changes twice per chip) 7 h qsum 9-2 . matched filter q output (changes twice per chip) 8 h power 9-2 . mf magnitude output, unsigned binary (changes twice per chip) 9 h isum 7-0 . mf viewport i output (changes twice per chip) a h qsum 7-0 . mf viewport q output (changes twice per chip) b h pk-isum 7-0 . mf peak i channel output (changes once per symbol) c h pk-qsum 7-0 . mf peak q channel output (changes once per symbol) d h dot 16-9 . dot product (changes once per symbol) e h cross 16-9 . cross product (changes once per symbol) f h txfbk 7-0 . loopback test output table 3. receiver test functions rxtest(0) (bits 2-0) rxtest(0) (bits 5-3) a tx cl o ck gener- at o r serial to dibit converter di f f erent i al enco der t x pn co de g enerat o rs nco complex multiplier mat ched filter power det ect o r viewport sin cos di bi t t o serial co nvert er di f f erent i al demodulator and carri er di scri mi nat o r txifclk txin txbitpls txtrkpls t xmchp rxiin 7-0 rxqin 7-0 rxo ut rxiout rxqout txtest(0) txtest(2) txtest(1) i & d filters a a a viewport a a rxtest(4) rxtest(5) a a peak ho l d a rxtest(9) a rxtest(a) a rxtest(7) a rxtest(6) a rxtest(b) a rxtest(c) aa rxtest(1) a rxtest(d) a rxtest(e) a a rxtest(3) rxtest(2) a rxtest(8) tx overlay generator rx overlay g enerat o r qpsk mo du- lator txifout 7-0 txiout txqout rxtest(f) a a figure 6: transmitter and receiver test points .com .com .com .com 4 .com u datasheet
21 STEL-2000A control registers downconverter registers address 00 h : bit 0 -- frequency control word load this bit is used to load a frequency control value into the nco, thereby changing its output frequency. the signal is internally synchronized to rxifclk to avoid intrinsic race or hazard timing conditions. the loading of the nco may be performed by various means. setting this bit provides a synchronized internal means to control update of the nco. alternatively, the mfld pin or the stel- 2000a?s programmable loop filter timing circuitry may be used. the mfld input and bit 0 of address 00 h are logically ored together so that, when either one is held low, a rising edge on the other triggers the frequency load function manually. the rising edge of this bit is synchronized internally so that, on the following sixth rising edge of rxifclk , the frequency control word is completely registered into the nco accumulator. the frequency load command must not be repeated until after a delay of six rxifclk cycles. address 01 h : bit 0 -- manual sample clock enable this bit selects the source of the internal baseband sampling clock, which should be at twice the nominal pn chip rate. the clock reference may be either sup- plied externally by rxmsmpl or generated inter- nally from rxifclk . when this bit is set high, the baseband sampling rate of the receiver is controlled by the external rxmsmpl signal. when it is set low, the sampling clock is generated internally (at a rate determined by the sample rate control counter and set by bits 5-0 of address 02 h ) and the rxmsmpl input is ignored. bit 1 -- invert loop filter value this bit allows the sign of the output signal from the loop filter to be inverted, thereby negating the value of the signal. the capability to invert the loop filter value permits the carrier frequency error component generated in the demodulator to be either added to or subtracted from the frequency control word of the nco. the correct setting will depend on several fac- tors, including whether high-side or low-side down- conversion is used. when this bit is set low, the loop filter output is negated before being summed with the frequency control word of the nco and is thus subtracted from the fcw; when this bit is set high, the loop filter out- put is not negated and is added to the fcw. bit 2 -- nco accumulator carry in this bit is primarily used as an internal test function and should be set low for normal operation. when this bit is set high, 1 lsb is added to the nco accu- mulator each clock cycle. when it is set low, the nco accumulator is not affected. bit 3 -- two's complement input the rxiin 7-0 and rxqin 7-0 input signals can be in either two's complement or offset binary formats. since all internal processing in the device operates with two's complement format signals, it is necessary to convert the rxiin 7-0 and rxqin 7-0 inputs in offset binary format to two?s complement format by invert- ing the msbs. when this bit is set high, the device expects two's complement format inputs on rxiin 7-0 and rxqin 7- 0 . when it is set low, the device expects offset binary format on rxiin 7-0 and rxqin 7-0 . in two's comple- ment format, the 8-bit input values range from e128 to +127 (80 h to 7f h ); in offset binary format, the values range from 0 to +255 (00 h to ff h ). bits 7-4 -- integrate and dump filter viewport control the STEL-2000A incorporates viewport (data selector) circuitry to select any three consecutive bits from the 14-bit output of the integrate and dump (i & d) fil- ters in the downconverter block as the 3-bit inputs to the dual-channel pn matched filter. the signal levels of the integrate and dump filter i and q outputs reflect the input signal levels and the number of sam- ples integrated before the filter contents are dumped, where the number of samples is deter- mined by the baseband sampling rate (nominally, twice the pn chip rate) and the i.f. sampling rate ( rxifclk ). setting the viewport thus effectively normalizes the i & d filter outputs before further processing. the unsigned value, n, of bits 7-4 of address 01 h determines the 3-bit inputs to the pn matched filter as the 14-bit i&d filter outputs divided by 2 n . equivalently, bits 7-4 control the viewport of the integrate and dump filter outputs as shown in table 5. note that viewport control affects both i and q channels of the integrate and dump filters. bits 7-4 i & d bits output to matched filter 0 h 2-0 1 h 3-1 .com .com .com .com 4 .com u datasheet
STEL-2000A 22 2 h 4-2 3 h 5-3 ..... .... ..... .... a h 12-10 b h 13-11 table 5. integrate & dump filter viewport control saturation protection is implemented for those cases when the integrate and dump filter output signal level overflows the scaled range selected for the pn matched filter. when the scaled value range is exceeded, the saturation protection limits the output word to the maximum or minimum value of the range according to whether the positive or negative boundary was exceeded. address 02 h : bits 5-0 -- receiver baseband sampling (dump) rate control the baseband sampling rate should be set to twice the nominal pn chip rate of the received signal and must be less than or equal to half the rate of rxifclk . when bit 0 of address 01 h is set low, the baseband sampling clock for the integrate and dump filter and all subsequent receiver circuitry is referenced to rxifclk and generated internally. the receiver baseband sampling rate is then set to the frequency of rxifclk /(n+1), where n is the value stored in bits 5- 0 and must range from 1 to 63. this feature is useful in cases where a specific sample rate is required that is an integer sub-multiple of f rxifclk . in cases where a sample rate is required that is not an integer sub- multiple of f rxifclk , an external baseband sampling rate can be provided by the rxmsmpl input. addresses 03 h through 06 h : nco frequency control word the STEL-2000A?s internal nco is driven by a fre- quency control word that is the sum of the frequency discriminator error value (generated in the demodula- tor) and the 32-bit frequency control word (fcw) stored in this location. the four 8-bit registers at addresses 03 h to 06 h are used to store the 32-bit fre- quency control word as shown in table 6. the lsb of each byte is stored in bit 0 of each register. addr 6 addr 5 addr 4 addr 3 bits 31-24 bits 23-16 bits 15-8 bits 7-0 table 6. nco fcw storage the nco frequency is then set by the fcw according to the following formula: f rxifclk x fcw f nco = eeeeeeeeeeeeee 2 32 in order to avoid in-band aliasing, f nco must not exceed 50% of f rxifclk ; normally, the fcw should be set so that f nco does not exceed ~35% of f rxifclk . while this limitation may seem to restrict use of the nco, higher i.f. transmit or receive frequencies can generally be achieved by using aliases resulting from digital sampling. the signal bandwidth with respect to f rxifclk , the modulation type, and the use of direct i.f. or quadrature sampling mode also restrict the choice of nco frequency, as discussed in appendix i. matched filter registers despreading of the received signal is accomplished in the STEL-2000A with a dual (i and q channel) pn matched filter. furthermore, the STEL-2000A is designed for burst signal operation, where each data burst begins with an acquisition/preamble symbol and is then followed by the actual information data symbols. two separate and independent pn codes can be employed, one for the acquisition/preamble symbol, the other for the information symbols. accordingly, the pn matched filter is supported by two pn code registers to independently allow the programming of two distinct codes up to 64 chips in length. the pn codes are represented as a sequence of ternary-valued tap coefficients, each requiring 2 bits of storage according to the mapping shown in table 7. tap bits 1,0 tap coeff. x0 0 01 +1 11 e1 table 7. pn matched filter tap values as a convention, tap 0 is the first tap as the received signal enters the pn matched filter, and tap 63 is the last. all active taps of the pn matched filter, from tap 0 up to tap (n-1), where n is the length of the pn code, should be programmed with tap coefficient values of +1 or -1 according to the pn code sequence. setting the end coefficients of the pn matched filter registers to zero values permits the effective length of the filter to be made shorter than 64 taps. addresses 07 h through 16 h : matched filter acquisition/preamble symbol coefficients addresses 07 h to 16 h contain the 64 2-bit acquisi- .com .com .com .com 4 .com u datasheet
23 STEL-2000A tion/preamble pn code coefficient values. the 128 bits of information are stored in 16 8-bit registers at addresses 07 h to 16 h as shown in table 8. address 16 h bits 7,6 bits 5,4 bits 3,2 bits 1,0 coeff. 63 coeff. 62 coeff. 61 coeff. 60 address 15 h bits 7,6 bits 5,4 bits 3,2 bits 1,0 coeff. 59 coeff. 58 coeff. 57 coeff. 56 address 08 h bits 7,6 bits 5,4 bits 3,2 bits 1,0 coeff. 7 coeff. 6 coeff. 5 coeff. 4 address 07 h bits 7,6 bits 5,4 bits 3,2 bits 1,0 coeff. 3 coeff. 2 coeff. 1 coeff. 0 table 8. acquisition/preamble coefficient storage addresses 17 h through 26 h : matched filter data symbol coefficients addresses 17 h to 26 h contain the 64 2-bit data sym- bol pn code coefficient values. the 128 bits of infor- mation are stored in 16 8-bit registers at addresses 17 h to 26 h as shown in table 9. the contents of addresses 17 h to 26 h are independent of and not affected by the contents of addresses 07 h to 16 h . address 26 h bits 7,6 bits 5,4 bits 3,2 bits 1,0 coeff. 63 coeff. 62 coeff. 61 coeff. 60 address 25 h bits 7,6 bits 5,4 bits 3,2 bits 1,0 coeff. 59 coeff. 58 coeff. 57 coeff. 56 address 18 h bits 7,6 bits 5,4 bits 3,2 bits 1,0 coeff. 7 coeff. 6 coeff. 5 coeff. 4 address 17 h bits 7,6 bits 5,4 bits 3,2 bits 1,0 coeff. 3 coeff. 2 coeff. 1 coeff. 0 table 9. data symbol coefficient storage address 27 h : bit 0 -- front end processor disable the front end processor (fep) averages the two baseband samples per chip by adding consecutive pairs of samples. the function may be disabled for test purposes by using this bit: when set low, the fep is enabled and in its normal mode of operation; when set high, the fep is disabled. power estimator registers address 28 h : bits 1-0 -- matched filter viewport control the STEL-2000A incorporates viewport (data selector) circuitry to select any eight consecutive bits from the 10-bit outputs of the pn matched filter as the 8-bit inputs to the power estimator and dpsk demodula- tor blocks. the symbol tracking processor, however, operates on the full 10-bit pn matched filter outputs before the viewport is applied. the signal levels of the pn matched filter output reflect the number of chips per symbol and the signal-to-noise ratio of the signal. setting the viewport thus effectively normal- izes the pn matched filter outputs prior to further processing. the unsigned value, n, of bits1-0 of address 28 h determines the 8-bit input to the power estimator and dpsk demodulator blocks as the 10-bit pn matched filter output divided by 2 n . equiva- lently, bits 1-0 control the viewport of the pn matched filter output as shown in table 10. note that viewport control affects both i and q channels of the pn matched filter output. bits 1-0 isum, qsum 0 0 bits 7-0 0 1 bits 8-1 1 x bits 9-2 table 10. matched filter viewport control saturation protection is implemented for those cases when the pn matched filter output signal level over- .com .com .com .com 4 .com u datasheet
STEL-2000A 24 flows the scaled range selected for the power estima- tor and dpsk demodulator. when the scaled value range is exceeded, the saturation protection limits the output word to the maximum or minimum value of the range according to whether the positive or nega- tive boundary was exceeded. acquisition and tracking processor registers the acquisition and tracking processor registers allow the user to configure how the pn matched fil- ter outputs for the acquisition/preamble symbol and the data symbols that follow thereafter are treated in the symbol tracking processor. since operation of the STEL-2000A receiver presumes symbol- synchronous pn modulation, processing of the pn matched filter outputs can be used for symbol synchronization prior to dpsk demodulation. the acquisition/preamble symbol and the data symbols may have different pn spreading codes, however, and so the pn matched filter outputs may exhibit different signal levels due to the different code lengths and autocorrelation properties. the control registers in this block allow such differences to be treated, as well as permitting specification of the number of receive data symbols per burst and other parameters associated with burst data communications. the i and q channel outputs of the pn matched filter are processed to estimate the correlation signal power at each baseband sampling instant. this estimated signal power is compared with the contents of the acquisition/preamble and data symbol threshold registers, as appropriate, to determine whether successful correlation has been detected. successful detection in acquisition mode immediately switches the receiver to despread and track the expected sub- sequent data symbols, while successful detection thereafter yields symbol synchronization. the thresh- old register values must be set by the user to satisfac- torily detect the correlation peak in noise obtained when the received pn-spread signal is corre lated against a local version of the pn code by the pn matched filter. once the power estimation value exceeds the threshold register value, a successful cor- relation is assumed to have been detected. further operations in the symbol tracking processor then handle the possibility of multiple detects per symbol, missed detects, etc. the choice of the threshold values will be determined by several factors. arithmetically, the digital base- band samples of the received signal are multiplied by the pn matched filter tap coefficients each baseband sample clock cycle and the results are summed to provide a correlation value. the i and q pn matched filter correlated output values are then used to esti- mate the signal power according to the following approximation: max{abs(i),abs(q)}+ 1 / 2 min{abs(i), abs(q)}. the magnitude of the estimated power thus depends on several variables, including the setting of the inte- grate and dump filter viewport, the pn code length and autocorrelation properties, and the magnitudes of the incoming rxiin 7-0 and rxqin 7-0 signals. the actual threshold values that should be programmed will therefore vary from application to application. addresses 29 h and 2a h : acquisition/preamble threshold addresses 29 h and 2a h contain the unsigned acqui- sition/preamble threshold value, as shown in table 11. this value is used for comparison with the esti- mated signal power from the pn matched filter to determine whether a successful correlation has been detected in acquisition mode. the acquisi- tion/preamble threshold value must be set by the user to satisfactorily detect the correlation peak in noise obtained when the received pn-spread acquisi- tion/preamble is correlated against a local version of the acquisition/preamble pn code by the pn matched filter. once the power estimation value exceeds the threshold value, a successful correlation is assumed to have been detected. note that the symbol tracking processor does not insert missed detect pulses when the device is in acquisition mode. addr 2a h addr 29 h bits 1-0 bits 7-0 acq. thresh. bits 9-8 acq. thresh. bits 7-0 table 11. acquisition/preamble threshold storage addresses 2b h and 2c h : data symbol threshold addresses 2b h and 2c h contain the data symbol threshold value, as shown in table 12. this value is used for comparison with the estimated signal power from the pn matched filter to determine whether a successful correlation has been detected for each data symbol. the data symbol threshold value must be set by the user to satisfactorily detect the correlation peak in noise obtained when the received pn-spread data symbol is correlated against a local version of the data symbol pn code by the pn matched filter. once the power estimation value exceeds the threshold value, a successful correlation is assumed to have been detected. if bit 2 of address 30 h is set low, then the symbol acquisition processor will insert a detect pulse at the appropriate time if a successful correla- tion is not detected as expected a priori . .com .com .com .com 4 .com u datasheet
25 STEL-2000A table 12. data symbol threshold storage address 2d h : bits 5-0 -- rx chips per data symbol the number of pn chips per data symbol in the receiver is controlled by address 2d h . the unsigned value must range from 1 to 63 (01 h to 3f h ), where the number of chips per data symbol will be this value plus 1. the a priori number of pn chips per data sym- bol, where this value must be equal to the number of non-zero coefficients stored in the data symbol coef- ficient registers (addresses 17 h to 26 h ) for the pn matched filter, is used to help control symbol timing in the receiver. since acquisition is purely based on correlation of a single received acquisition/preamble symbol, the corresponding number of chips per acquisition/preamble symbol is not required and no similar register is provided for such use. address 2e h : receiver data symbols per burst (bits 7-0) the data stored as two bytes in addresses 2e h (ls byte) and 3a h (ms byte) defines the number of data symbols per burst. this unsigned value must range from 3 to 65,535 (0003 h to ffff h ), and the number of data symbols per burst will be this value minus 2, giving a range of 1 to 65,533. note that the range is slightly different from that supported by the stel- 2000a?s transmitter. once the number of received data symbols processed exceeds this number, the burst is assumed to have ended and the receiver immedi ately returns to acquisition mode, ready for the next burst. address 2f h : missed detects per burst threshold to monitor the reception quality of the received burst data symbols, the STEL-2000A incorporates a feature within its tracking algorithm that tallies the number of received data symbols whose pn matched filter correlation output did not exceed the data symbol threshold value. whenever a "missed detect" occurs, the tracking algo- rithm will generate and insert a detect signal at the sample clock cycle corresponding to the expected cor- relation peak in order to maintain a continuous train of data symbols and symbol clocks. simultaneously, a "missed detect" pulse will be generated internally and tallied for the current burst. when the accumulated number of missed detects is greater than the value stored in address 2f h , the device will terminate reception of the current burst and return to acquisition mode to await the next burst. the unsigned value in address 2f h must range from 1 to 255 (01 h to ff h ), where this value is the maximum number of missed detects per burst allowed before the burst terminates. this function can be disabled by setting bit 5 of address 30 h high. address 30 h : bit 0 -- manual detect enable while the receiver is in acquisition mode, valid bursts may be ignored by setting this bit high. when it is set low (normal operation), the detection of a burst's acquisition/preamble symbol is enabled. setting this bit high allows the user to force the device to ignore acquisition/preamble symbols that would normally be successfully acquired. this feature could be used, for example, in a system employing multiple receivers with identical pn codes in a time division multiple access scheme where time-synchronized device man- agement could be supported through dynamic setting of this bit. bit 1 -- manual punctual this bit enables the user to completely disable the internal tracking circuitry and force symbol informa- tion to be transferred to the demodulator punctually at the symbol rate determined by the number of chips per data symbol information programmed into address 2d h . this function overrides the symbol tracking algorithm, although the absence of a success- ful correlation will continue to be tallied as a missed detect and compared against the value stored in address 2f h to monitor signal quality unless disabled by bit 5 of address 30 h . when bit1 is set low, the STEL-2000A will operate in its normal mode with symbol timing derived from the symbol tracking pro- cessor; when set high, symbol timing is derived from the a priori number of chips per data symbol stored in bits 5-0 of address 2d h . bit 2 -- force continuous acquisition this bit enables the user to force the receiver to remain in acquisition mode even after successful detection of the acquisition/preamble symbol. when so commanded, the receiver will continuously process only acquisition/preamble symbols and will not switch from acquisition mode. this function may be used under manual control to receive a series of repeated acquisition/preamble symbols in order to increase the confidence level of burst detection before beginning demodulation of the data symbol informa- tion. addr 2c h addr 2b h bits 1-0 bits 7-0 data thresh. bits 9-8 data thresh. bits 7-0 .com .com .com .com 4 .com u datasheet
STEL-2000A 26 when this bit is set high, the device will be locked in acquisition mode and the symbol tracking processor will not insert missed detect pulses; when set low, normal operation will be enabled whereby data sym- bols are automatically processed immediately follow- ing detection of an acquisition/preamble symbol. bit 3 -- bypass max. power selector the STEL-2000A?s receiver acquisition and tracking circuitry includes a function that continuously selects the highest estimated power level out of the three most recent consecutive estimated power levels from the pn matched filter. as the contents of the sliding 3-sample window change each cycle of the baseband sampling clock, a new determination of the highest power level is made from the current set of the three most recent power level values. the correlated i and q channel values within the 3-sample window corre- sponding in time to the highest observed power level are then available to be processed in the demodulator. this function assures that, within any 3-sample period, the i and q channel values corresponding to the highest estimated power level will be selected over the two other pairs of correlated values even if the estimated power levels of the other pairs exceed the programmed threshold. the maximum power selector is used in normal operation of the stel- 2000a so that the tracking algorithm discriminates by estimated power levels rather than exact timing inter- vals, thereby allowing the receiver to adjust to dyna- mic changes of the symbol phase. in cases where spe- cific correlation values are desired regardless of their associated power level, bit 3 of address 30 h enables the 3-sample power discriminator to be bypassed, thereby making the outputs of the pn matched filter available directly to the demodulator. when this bit is set high, the maximum power selec- tor is bypassed; when it is set low, the selector is enabled, where this is the normal operating mode. bit 4 -- half symbol pulse off the STEL-2000A generates two bit clock pulses per symbol when operating in qpsk mode, one at the mid-point of each symbol and one at the end of each symbol. these clocks are used by the output proces- sor to manage data flow. when this bit is set high, the mid-point pulse is sup- pressed; when it is set low, the device operates in its normal mode. this function is primarily used for test purposes and should not normally be used. bit 5 -- missed detects per burst off to monitor the quality of the received burst data symbols, the symbol tracking processor keeps track of the cumulative number of received data symbols per burst whose estimated correlation power level did not exceed the specified data symbol threshold value. when the accumulated number of missed detects equals the missed detects per burst threshold value stored in address 2f h , the device will terminate the reception of the current burst with the next missed detect and return to acquisition mode to await the next burst. when bit 5 is set low, the "missed detect" function operates normally; when set high, this function is dis- abled, allowing the device to be operated until the end of the specified data burst even when the number of missed detects exceeds the missed detects per burst threshold. bit 6 -- receiver symbols per burst off the data stored in addresses 2e h and 3a h defines the number of data symbols per burst that will be pro- cessed by the receiver. this unsigned value must range from 3 to 65,535 (0003 h to ffff h ), and the number of data symbols per burst will be this value minus 2. once the number of data symbols processed by the receiver exceeds this number, the burst is assumed to have ended and the receiver will immedi- ately return to acquisition mode. when bit 6 is set high, the function is disabled, pro- viding an option to track data symbols under external control for bursts of more than 65,533 data symbols or indefinitely for continuous transmission; when set low, the function will operate normally as defined by the value stored in addresses 2e h and 3a h . address 31 h : bit 0 -- manual detect pulse this bit provides the user a means to externally gen- erate symbol timing, bypassing and overriding the internal symbol power estimation and tracking cir- cuitry. this function may be useful in applications where the dynamic characteristics of the transmission environ ment require unusual adjustments to the symbol timing. when bit 0 of address 30 h is set high (manual detect enable) and when rxmdet is low, a rising edge on this bit will generate a detect pulse. the function can also be performed by means of the rxmdet input signal. bit 0 of address 31 h and the rxmdet input are logically ored together so that, when either one is held low, a rising edge on the other triggers the man- ual detect function. the rising edge of this bit is syn- chronized internally so that on the second rising edge .com .com .com .com 4 .com u datasheet
27 STEL-2000A of the baseband sampling clock that follows, the rising edge of bit 0 will transfer the i and q channel correlated output values of the pn matched filter to the dpsk demodulator. address 32 h : bit 0 -- receiver manual abort this bit enables the user to manually force the stel- 2000a to cease reception of the present burst of data symbols and prepare for acquisition of a new burst. this function can be used to reset the receiver and prepare to receive a priority transmission signal under precise timing control, giving the user the abil- ity to control the current state of the receiver as needed. when rxmabrt is set low, a rising edge on bit 0 of address 32 h will execute the abort function. the function can also be performed by means of the rxmabrt input. the rxmabrt input and bit 0 of address 32 h are logically ored together so that, when either one is held low, a rising edge on the other trig- gers the abort function. the second rising edge of the internal baseband sampling clock that follows a rising edge of this bit will execute the abort and also clear the symbols-per-burst, samples-per-symbol, and missed-detects-per-burst counters. the counters will be reactivated on the detection of the next acquisi- tion/preamble symbol or by a manual detect signal. demodulator registers address 33 h : bits 1-0 -- signal rotation control these bits control the function of the signal rotation block used in demodulation of the differentially encoded bpsk, qpsk, or p /4 qpsk signals. the previous symbol will be rotated in phase with respect to the current symbol as shown in table 13, where i out and q out are the i and q channel outputs of the signal rotation block and i in and q in are the inputs. the normal settings are 0 x (no rotation) for bpsk and p /4 qpsk signals and 1 1 (e45 rotation) for conventional qpsk signals. bits 1,0 i out q out resulting rotation 0 x i in q in no rotation 1 0 i in e q in q in + i in +45 rotation 1 1 i in + q in q in e i in e45 rotation table 13. signal rotation control bit 2 -- not used bit 2 of address 33 h is not used and should always be set low. bit 3 -- loop clear disable the setting of this bit determines whether the loop filter's k2 accumulator is reset or not when the stel- 2000a receiver function is turned off when the input signal mrxen is set low. when bit 3 is set low, the loop filter's k2 accumula- tor will be reset to zero whenever mrxen is set low to disable the receiver function. when bit 3 is set high, this function is disabled and the contents of the accumulator are not affected when mrxen transi- tions from high to low. the optimum setting of this bit will depend on the stability of the oscillators used for carrier generation and frequency translation in the system and the length of the period between bursts. if the oscillators are stable and the period between bursts is not very long, the optimum setting of this bit will be low so that at the start of each burst the track- ing loop will resume from its state at the end of the previous burst. if the oscillators are not stable or if the period between bursts is long with respect to the oscillators? stability, then the optimum setting may be high so that the tracking loop will restart from its ini- tial state at the start of each burst. bits 7-4 -- afc viewport control the STEL-2000A incorporates viewport (data selector) circuitry to select any eight consecutive bits from the 17-bit output of the frequency discriminator as the 8-bit input to the loop filter block to implement the STEL-2000A?s afc function. the unsigned value, n, of bits7-4 of address 33 h determines the 8-bit input to the loop filter as the 17-bit frequency discriminator output divided by 2 n . equivalently, bits 7-4 control the viewport of the frequency discriminator output as shown in table 14. bits 7-4 discrim. bits output to loop filter 0 h 7-0 1 h 8-1 2 h 9-2 3 h 10-3 8 h 15-8 9 h 16-9 a h - f h not used table 14. afc viewport control saturation protection is implemented for those cases when the frequency discriminator output signal level .com .com .com .com 4 .com u datasheet
STEL-2000A 28 overflows the scaled range selected for the loop fil- ter. when the scaled value range is exceeded, the sat- uration protection limits the output word to the max- imum or minimum value of the range according to whether the positive or negative boundary was exceeded. address 34 h : bits 4-0 -- k2 gain value bits 4-0 control the gain factor k2 within the loop fil- ter. the gain factor multiplies the signal before the k2 accumulator by a value of 2 n , where n is the 5-bit k2 gain value. the value must range from 0 to 21 (15 h ) as shown in table 15. bits 4-0 gain in k2 path 00 h 2 0 01 h 2 1 ..... .... ..... .... 14 h 2 20 15 h 2 21 table 15. k2 gain values bit 5 -- k2 on this bit enables or disables the k2 path of the loop filter. setting this bit low resets the k2 accumulator and keeps it reset; setting this bit high enables the path and turns on k2. bit 6 -- carry in one half when this bit is set high, the value of 1 / 2 of an lsb is added to the accumulator of the k2 path of the loop filter each symbol period. this function can be useful in cases where the scale and gain functions that pre- cede the accumulator produce quantized values with significant error. in such cases, the processing of two's complement numbers by the accumulator will compound the error over time. since truncation of two's complement numbers leads to a negative bias of 1 / 2 of an lsb when the error is random, adding 1 / 2 of an lsb per symbol can compensate by averaging the error to zero. when bit 6 of address 34 h is set high, a value of 1 / 2 will be added to the accumulator input each symbol cycle; when it is low, a zero will be added. address 35 h : bits 4-0 -- k1 gain value bits 4-0 control the gain factor k1 within the loop fil- ter. the gain factor multiplies the signal by a value of 2 n , where n is the 5-bit k1 gain value. the value must range from 0 to 21 (15 h ), as shown in table 16. bits 4-0 gain in k1 path 00 h 2 0 01 h 2 1 ..... .... ..... .... 14 h 2 20 15 h 2 21 table 16. k1 gain values bit 5 -- k1 on this bit enables or disables the k1 path of the loop filter. setting this bit low disables the k1 path; set- ting this bit high enables the path and turns on k1. bit 6 -- freeze loop this bit enables the loop filter to be held constant during symbol cycles, thereby fixing the output fre- quency of the nco at the value established by the loop filter when bit 6 was set high. this function can be useful in cases where a carrier offset has been tracked by the loop filter and additional doppler off- sets are to be ignored. when this bit is set high, it freezes the output of the loop filter; when it is set low, the loop filter is enabled and processes the frequency error informa- tion in the usual way. output processor control registers address 36 h : bit 0 -- reverse i and q in qpsk mode, the order in which the received i and q bit information is output may be reversed by set- ting this bit high. this function has the effect of inter- changing i and q channels. normally, when this bit is set low, the i-channel bit will precede the q-channel bit in each symbol period. when bit 0 is set high, the q-channel bit will precede the i-channel bit each sym- bol period. bit 1 -- bpsk enable this bit configures the output processor to output either one bit per symbol (bpsk mode) or two bits per symbol (qpsk mode). in addition, it enables the user to output the i-channel information only or the q- channel information only, depending on the value of bit 0. table 17 shows the configuration of the output processor for all combinations of the values of bits 0 and 1. bit 1 bit 0 output processor mode 0 0 qpsk mode with i-channel bit preceding q-channel bit .com .com .com .com 4 .com u datasheet
29 STEL-2000A 0 1 qpsk mode with q-channel bit preceding i-channel bit 1 0 bpsk mode with i-channel information output 1 1 bpsk mode with q-channel information output table 17. output processor modes bit 1 also sets the frequency discriminator into either bpsk or qpsk mode. the STEL-2000A receiver uses dot and cross product results generated within the dpsk demodulator to develop the error signal used to form a closed-loop afc for carrier frequency acquisition and tracking. when bit 1 is set high, the discriminator circuitry is in bpsk mode and the frequency discriminator func- tion is calculated as: cross 16-0 x dot msb . when bit 1 is set low, the discriminator circuitry is in qpsk mode and the frequency discriminator func- tion is calculated as: (cross 16-0 x dot msb ) e (dot 16-0 x cross msb ). bit 2 -- invert output this bit inverts the output bits of both the i and q channels. the inversion will occur at the output pins rxout , rxiout , and rxqout . when this bit is set low, the outputs are not inverted; when it is set high, the outputs are inverted. address 37 h : bit 0 -- nco enable the function of this bit is to allow the power con- sumed by the operation of the nco circuitry to be minimized when the STEL-2000A is not receiving. the nco can also be disabled while the STEL-2000A is transmitting provided that the STEL-2000A?s on- chip bpsk/qpsk modulator is not being used. with the instantaneous acquisition properties of the pn matched filter, it is often desirable to shut down the receiver circuitry to reduce power consumption, resuming reception periodically until an acquisi- tion/preamble symbol is acquired. setting bit 0 low will do this by holding the nco in a reset state. after this bit has been set high again to re-activate the nco it will be necessary to reload the frequency control word into the nco. note that this bit operates inde- pendently of bits 1 ( transmitter enable) and 2 (receiver enable) , which have similar control over the transmit and receive circuits, respectively. bit 0 of address 37 h performs the same function as mncoen , and these two signals are logically ored together to form the overall control function. when this bit is set low, mncoen controls the activity of the nco circuitry and, when mncoen is set low, bit 0 controls the activity of the nco circuitry. when either bit 0 or mncoen (whichever is in control, as defined above) goes low, a reset sequence occurs on the following rxifclk cycle to virtually disable all of the nco circuitry, although the user pro- grammable control registers are not affected by the power down sequence. upon reactivation (when either mncoen or bit 0 of address 37 h return high), the nco must be reloaded with frequency control information either by means of the mfld input or by writing 01 h into address 00 h . bit 1 -- transmitter enable a rising edge on this bit causes the transmit sequence to begin so that the STEL-2000A first transmits a sin- gle acquisition/preamble symbol followed by data symbols. bit 1 of address 37 h should be set low after the last symbol has been transmitted to minimize power consumption of the transmitter circuit. bit 1 of address 37 h operates independently of bits 2 and 0, where those bits have similar control over the receive and nco circuitry, respectively. when input signal mtxen is set low, bit 1 of address 37 h controls the activity of the transmit circuitry and, when mtxen is set low, bit 1 controls this function. when either bit 1 or mtxen (whichever is in control, as defined above) goes low, a reset sequence occurs on the following txifclk cycle to virtually disable all of the transmitter data path, although the user programmable control registers are not affected by the power down sequence. bit 2 -- receiver enable the function of this bit is to allow power consumed by the operation of the receiver circuitry to be mini- mized when the device is not receiving. with the instantaneous acquisition properties of the pn matched filter, it is often desirable to shut down the receiver circuitry to reduce power consumption, resuming reception periodically until an acquisi- tion/preamble symbol is acquired. setting bit 2 low reduces the power consumption substantially. when bit 2 is set high, the receiver will automatically power up in acquisition mode regardless of its prior state when it was powered down. bit 2 of address 37 h operates independently of bits 1 and 0 of address 37 h ,where these signals have similar control over the transmit and nco circuitry, respectively. bit 2 of address 37 h performs the same function as mrxen , and these two signals are logically ored together to form the overall control function. when bit 2 of address 37 h is set low, mrxen controls the activity of the receiver circuitry and, when mrxen is set low, bit 2 of address 37 h controls the activity of the receiver circuitry. when either bit 2 or mrxen .com .com .com .com 4 .com u datasheet
STEL-2000A 30 (whichever is in control, as defined above) goes low, a reset sequence begins on the following rxifclk cycle and continues through a total of six rxifclk cycles to virtually disable all of the receiver data paths, although the user programmable control regis- ters are not affected by the power down sequence. note that this reset sequence will also reset the con- tents of address 38 h to 0. if the rxtest 7-0 bus is being used for reading any function except the matched filter i and q inputs the value required must be re-written after re-enabling the receiver. address 38 h : bits 3-0 -- rxtest 7-0 function select the data stored in bits 3-0 of address 38 h selects the signal available at the rxtest 7-0 bus (pins 41-48). these pins provide access to 16 test points within the receiver according to the data stored in bits 3-0 of address 38 h and the assignments shown in table 3. note that the validity of the rxtest 7-0 bus signals at rxifclk frequencies over 20 mhz is dependent on the function selected. functions that change more rapidly than once per symbol may be indeterminate at clock frequencies higher than 20 mhz. note that the reset sequence that occurs whenever the receiver is disabled will also reset the contents of address 38 h to 0. if the rxtest 7-0 bus is being used for reading any function except the matched filter i and q inputs the value required must be re-written after disabling the receiver. address 39 h : bits 6-0 -- matched filter power saver the data stored in bits 6-0 of address 39 h allows the unused sections of the pn matched filter to be turned off when the pn matched filter is configured to be less than 64 taps long for data symbols. all taps are always fully powered when the device is in acquisition mode. the pn matched filter is split into seven 9-tap sec- tions, and the power to each section is controlled by the settings of bits 6-0 of address 39 h , as shown in table 18. bit in addr. 39 h mf taps controlled 0 1-9 1 10-18 2 19-27 3 28-36 4 37-45 5 46-54 6 55-63 table 18. matched filter tap power control power control is not provided for tap 0, the first tap of the pn matched filter, since tap 0 is always used no matter what the pn code length. setting a bit high in bits 6-0 of address 39 h turns off the power to the corresponding block of taps of the pn matched filter. the power should only be turned off to those blocks of taps for which all the tap coefficients in that block have been set to zero address 3a h : receiver data symbols per burst (bits 15-8) the data stored as two bytes in addresses 2e h (ls byte) and 3a h (ms byte) defines the number of data symbols per burst. this unsigned value must range from 3 to 65,535 (0003 h to ffff h ), and the number of data symbols per burst will be this value minus 2, giving a range of 1 to 65,533. note that the range is slightly different from that in the transmitter. once the number of received data symbols processed exceeds this number, the burst is assumed to have ended and the STEL-2000A immediately returns to acquisition mode to await the next burst. address 3b h : bit 0 -- matched filter loopback enable the STEL-2000A incorporates a loopback capability that feeds the encoded and spread transmit signals txiout and txqout directly into the pn matched filter inputs. this test mode allows the baseband portion of the system to be tested independently of the bpsk/qpsk modulator and downconverter. setting bit 0 of address 3b h high enables this loop- back path; setting it low puts the device into its nor- mal operating mode. bit 1 -- i.f. loopback enable the STEL-2000A incorporates a loopback capability that feeds the encoded, spread and modulated trans- mit signal txifout 7-0 directly into the receiver rxiin 7-0 input. this test mode allows the entire digi- tal portion of the system to be tested. since only the i channel is provided as an input, i.f. loopback requires that the pn chip rate and rxifclk rate be consistent with direct i.f. sampling mode. setting bit 1 of address 3b h high enables this loop- back path; setting it low puts the device into its normal operating mode. bits 3-2 -- receiver overlay select the STEL-2000A incorporates programmable overlay code generators in both the transmitter and receiver. when enabled, the selected receiver overlay code is subtracted from the data symbols, one overlay bit per symbol in both bpsk and qpsk modes. no synchro- nization beyond the burst acquisition synchronization that is intrinsic to operation of the STEL-2000A is .com .com .com .com 4 .com u datasheet
31 STEL-2000A required since the overlay code generators in both the transmitter and the receiver are automatically reset at the start of each burst. the addition of the overlay code randomizes the transmitted data sequence to guarantee that the spectrum of the transmitted signal will be adequately whitened and will not contain a small number of spectral lines even when the data itself is not random. three transmit and receive overlay codes can be selected, where they are each maximal length sequences with lengths of 63, 511 and 1023 symbols. the receiver overlay codes are enabled and selected by the settings of bits 3-2 of address 3b h , as shown in table 19. bits 3-2 in addr. 3b h overlay code length and polynomial 0 overlay code disabled 1 63: 1 + x 2 + x 3 + x 5 + x 6 2 511: 1 + x 2 + x 3 + x 5 + x 9 3 1023: 1 + x 2 + x 3 + x 5 + x 10 table 19. receiver overlay code select addresses 3c h to 3f h are unused. transmit control registers address 40 h : bit 0 -- transmit bpsk this bit configures the transmitter for either bpsk or qpsk mode transmission. and differential encoding. if programmed for bpsk mode, data is requested by the STEL-2000A by a rising edge of output signal txbitpls , where txbitpls is generated once per symbol, one chip period before the end of the current symbol. at the end of the symbol duration, the txin data is latched into the device. txbitpls falls low immediately following the rising edge of txifclk , which latches the txin value, and is generated repeatedly at the symbol rate as long as the input sig- nal mtxen remains high. in qpsk mode, data is requested by the STEL-2000A by a rising edge of output signal txbitpls , where this signal is generated in this mode twice per symbol, first one chip period before the middle of the symbol and then one chip period before the end of the symbol. txbitpls requests the data exactly one chip cycle before latching the txin data into the device. txbitpls falls low immediately following the rising edge of txifclk , which latches the txin value. when bit 0 of address 40 h is set low, the transmitter is configured in qpsk mode; when it is set high, the transmitter is configured in bpsk mode. bit 1 -- offset binary output the txifout 7-0 output signals can be in either two's complement or offset binary formats. since all inter- nal processing in the device uses two's complement format signals, the msb of the two?s complement modulated transmitter output must be inverted if the output is to be in offset binary format. when this bit is set high, the txifout 7-0 output will be in offset binary format and, when it is set low, the signal will be in two?s complement format. in two's complement format, the 8-bit output values range from e128 to +127 (80 h to 7f h ); in offset binary for- mat, the values range from 0 to +255 (00 h to ff h ). bit 2 -- manual chip clock enable this bit enables the pn chip rate to be controlled by either the internal chip rate clock generator or by the external input signal txmchp . the txmchp input allows the user to manually insert a single pn chip clock pulse or continuous stream of pulses. this fea- ture is useful in cases where a specific chip rate is required that cannot be derived by the internal clock generator which generates clocks of integer sub-mul- tiples of the frequency of txifclk . the signal is internally synchronized to txifclk to avoid race or hazard timing conditions. when this bit is set high, txmchp will provide the pn chip rate clock; when it is set low, the clock will be provided by the internal chip rate clock generator controlled by bits 5-0 of address 41 h . bit 3 -- invert symbol this bit allows the user to invert the i and q channel bits following differential encoding and before being spread by the pn code. this function has the same effect as inverting the pn code, which may be useful in some cases. when this bit is set high, the encoded i and q channel bits will be inverted; when it is set low, the i and q channel bits will not be inverted. address 41 h : bits 5-0 -- txifclk cycles per chip bits 5-0 set the transmitter baseband pn chip rate to the frequency of txifclk /(n+1), where n is the value stored in bits 5-0. the value of the data stored in bits 5-0 must range from 1 to 63 (01 h to 3f h ). this feature is useful when the pn chip rate required is an integer sub-multiple of the frequency of txifclk . in cases where a chip rate is required that is not an inte- ger sub-multiple of the frequency of txifclk , the rate may be controlled externally using txmchp . address 42 h : .com .com .com .com 4 .com u datasheet
STEL-2000A 32 bits 5-0 -- tx chips per data symbol the number of chips per data symbol in the transmit- ter is stored in bits 5-0 of address 42 h . the unsigned value must range from 1 to 63 (01 h to 3f h ), and the number of chips per data symbol will be this value plus 1. this value controls data symbol timing in the transmitter. address 43 h : bits 5-0 -- tx chips per acquisition/preamble symbol the number of chips per acquisition/preamble sym- bol in the transmitter is stored in bits 5-0 of address 43 h . the unsigned value must range from 1 to 63 (01 h to 3f h ), and the number of chips per data sym- bol will be this value plus 1. this value controls the acquisi tion/preamble symbol timing in the transmitter. addresses 44 h through 4b h : transmitter acquisition/preamble symbol code each STEL-2000A burst transmission begins with an acquisition/preamble symbol and is then followed by the actual information data symbols. two separate and independent pn codes can be employed, one for the acquisition/preamble symbol, the other for the information symbols. accordingly, the STEL-2000A transmit pn code generators, like the receiver?s pn matched filter, support independent pn codes up to 64 chips in length for the two modes. addresses 44 h to 4b h contain the binary transmitter acquisi- tion/preamble symbol pn code chip values, where the configuration of the stored bits is as shown in table 20. addr 4b h , bits 7-0 code bits 63-56 ............. ............. addr 45 h , bits 7-0 code bits 15-8 addr 44 h , bits 7-0 code bits 7-0 table 20. acquisition/preamble symbol codes the length, n, of the acquisition/preamble symbol code is set by the value of (n-1) stored in bits 5-0 of address 43 h . an internal counter begins the transmis- sion with the pn code chip corresponding to that value. the last chip transmitted per symbol is then code chip 0. note that this convention agrees with that used for the STEL-2000A?s pn matched filter: for a code of length n, code chip (n-1) will be the first chip transmitted and will first be processed by tap 0 of the pn matched filter; the last chip per symbol to be transmitted, however, will be chip 0, and at that time chip (n-1) will be processed by tap(n-1) and chip 0 by tap 0 to achieve peak correlation. opera- tion with the subsequent data symbols is analogous. address 4c h through 53 h : data symbol code addresses 4c h to 53 h contain the binary data symbol pn code sequence values. the storage capacity, assignments, and operation are similar to that of the acquisition/preamble pn code sequence values. the configuration of the bits stored is shown in table 21. addr 53 h , bits 7-0 code bits 63-56 ............. ............. addr 4d h , bits7-0 code bits 15-8 addr 4c h , bits 7-0 code bits 7-0 table 21. data symbol codes address 54 h : bits 1-0 -- transmitter overlay select the STEL-2000A incorporates programmable overlay code generators in both the transmitter and receiver. when enabled, the selected transmitter overlay code is subtracted from the data symbols, one overlay bit per symbol in both bpsk and qpsk modes. no syn- chronizat ion is required since the codes in both the transmitter and the receiver are automatically syn- chronized by resetting the code generators at the start of each burst. the addition of the overlay codes ran- domizes the transmitted data sequence to guarantee that the spectrum of the transmitted signal will be adequately whitened and will not contain a small number of spectral lines even when the data itself is not random. three transmit and receive overlay codes can be selected, where they are each maximal length sequences with lengths of 63, 511 and 1023 symbols. the transmitter overlay codes are enabled and selected by the settings of bits 1-0 of address 54 h , as shown in table 22. .com .com .com .com 4 .com u datasheet
33 STEL-2000A bits 1-0 in addr. 54 h overlay code length and polynomial 0 overlay code disabled 1 63: 1 + x 2 + x 3 + x 5 + x 6 2 511: 1 + x 2 + x 3 + x 5 + x 9 3 1023: 1 + x 2 + x 3 + x 5 + x 10 table 22. transmitter overlay code select bit 2 -- not used this bit should be set to zero at all times. address 55 h through 56 h : transmitter data symbols per burst (bits 15-0) the data stored as two bytes in addresses 55 h (ls byte) and 56 h (ms byte) defines the number of data symbols per burst for the transmitter. this unsigned value must range from 1 to 65,535 (0001 h to ffff h ) for burst mode operation, and the number of data symbols per burst will be this value plus 1. note that the range is slightly different from that in the receiver. once the number of transmitted data symbols exceeds this number, the burst is assumed to have ended and the transmitter is immediately turned off. if the data value is set to 0000 h the symbols per burst counter is disabled, permitting the STEL-2000A to be used for continuous transmission of data. register setting sequence the majority of the registers are completely indepen- dent and can be set or modified in any order. how- ever, there are inter-relationships between the settings of bits 2 and 0 in address 37 h with the data in address 38 h , and the need to reload the nco after enabling it, respectively. consequently, any time the data in address 37 h is modified it will be necessary to attend to both of these functions again. setting bit 2 low in address 37 h will cause the data in address 38 h to be set to zero. therefore, if the rxtest 7-0 bus is being used for reading any function except the matched filter i and q inputs the value required must be re-written after re-enabling the receiver. setting the mrxen input low will have the same effect as setting bit 2 low in address 37 h , requiring address 38 h to be rewritten after it is set high again. similarly, setting bit 0 in address 37 h low will hold the nco in a reset state, and after this bit has been set high again it will be necessary to reload the nco either by writing 01 h into address 00 h or with a rising edge on the mfld input. setting the mncoen input low will have the same effect as setting bit 0 low in address 37 h , requir- ing the nco to reloaded after it has been re-enabled. .com .com .com .com 4 .com u datasheet
STEL-2000A 34 decimal, hex and binary address equivalents dec. hex. binary dec. hex. binary dec. hex. binary 000 h 0000000 101 h 0000001 202 h 0000010 303 h 0000011 404 h 0000100 505 h 0000101 606 h 0000110 707 h 0000111 808 h 0001000 909 h 0001001 10 0a h 0001010 11 0b h 0001011 12 0c h 0001100 13 0d h 0001101 14 0e h 0001110 15 0f h 0001111 16 10 h 0010000 17 11 h 0010001 18 12 h 0010010 19 13 h 0010011 20 14 h 0010100 21 15 h 0010101 22 16 h 0010110 23 17 h 0010111 24 18 h 0011000 25 19 h 0011001 26 1a h 0011010 27 1b h 0011011 28 1c h 0011100 29 1d h 0011101 30 1e h 0011110 31 1f h 0011111 32 20 h 0100000 33 21 h 0100001 34 22 h 0100010 35 23 h 0100011 36 24 h 0100100 37 25 h 0100101 38 26 h 0100110 39 27 h 0100111 40 28 h 0101000 41 29 h 0101001 42 2a h 0101010 43 2b h 0101011 44 2c h 0101100 45 2d h 0101101 46 2e h 0101110 47 2f h 0101111 48 30 h 0110000 49 31 h 0110001 50 32 h 0110010 51 33 h 0110011 52 34 h 0110100 53 35 h 0110101 54 36 h 0110110 55 37 h 0110111 56 38 h 0111000 57 39 h 0111001 58 3a h 0111010 59 3b h 0111011 60 3c h 0111100 61 3d h 0111101 62 3e h 0111110 63 3f h 0111111 64 40 h 1000000 65 41 h 1000001 66 42 h 1000010 67 43 h 1000011 68 44 h 1000100 69 45 h 1000101 70 46 h 1000110 71 47 h 1000111 72 48 h 1001000 73 49 h 1001001 74 4a h 1001010 75 4b h 1001011 76 4c h 1001100 77 4d h 1001101 78 4e h 1001110 79 4f h 1001111 80 50 h 1010000 81 51 h 1010001 82 52 h 1010010 83 53 h 1010011 84 54 h 1010100 85 55 h 1010101 86 56 h 1010110 table 23. decimal, hexadecimal and binary address equivalents .com .com .com .com 4 .com u datasheet
35 STEL-2000A register summary address contents bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 h nco load 01 h integrate & dump filter viewport control 2?s c. input nco c?in inv. lf rxmsmpl 02 h receiver baseband sampling rate control 03-06 h nco frequency control word (32 bits) 07-16 h matched filter acquisition/preamble symbol coefficients 17-26 h matched filter data symbol coefficients 27 h fep disable 28 h mf viewport control 29-2a h acquisition/preamble symbol threshold, bits 9-0 2b-2c h data symbol threshold, bits 9-0 2d h receiver chips per data symbol 2e h receiver data symbols per burst, bits 7-0 2f h missed detects per burst threshold 30 h rx symb./ burst off missed det. per bst. off half symb. pulse off b ? pass max. power sel. force cont. acquis. manual punctual man. det. enable 31 h man. det. 32 h man. abort 33 h afc viewport control lf clr. dis unused (0) signal rotation contrl. 34 h carry in 1/ 2 k2 on k2 gain value 35 h lf freeze k1 on k1 gain value 36 h inv. o/p bpsk en. rev. i & q 37 h rx. en. tx en. nco en. 38 h rxtest 7-0 read address 39 h matched filter power saver 3a h receiver data symbols per burst, bits 15-8 3b h receiver overlay sel. if lpbk en mf lpbken 3c-3f h 40 h inv. symb. txmchp o?bin. o/p tx bpsk 41 h txifclk cycles per chip 42 h tx chips per data symbol 43 h tx chips per acquisition/preamble symbol 44-4b h transmitter acquisition/preamble symbol code (64 bits) 4c-53 h transmitter data symbol code (64 bits) 54 h set to 0 transmitter overlay sel. 55-56 h transmitter data symbols per burst, bits 15-0 .com .com .com .com 4 .com u datasheet
STEL-2000A 36 table 24. register summary .com .com .com .com 4 .com u datasheet
37 STEL-2000A electrical characteristics absolute maximum ratings note: stresses greater than those shown below may cause permanent damage to the device. exposure of the device to these conditions for extended periods may also affect device reliability. all voltages are referenced to v ss . symbol parameter range units t stg storage temperature e55 to +150 c v ddmax supply voltage on v dd e0.3 to + 7 volts v i(max) input voltage e0.3 to v dd +0.3 volts i i dc input current 10 ma recommended operating conditions symbol parameter range units v dd supply voltage +5 5% volts t a operating temperature (ambient) 0 to +70 c d.c. characteristics operating conditions: v dd = 5.0 v 5%, v ss = 0 v, t a = 0 to 70 c symbol parameter min. typ. max. units conditions i ddq supply current, quiescent 5.0 ma static, no clock i dd supply current, operational (transmitter + receiver) 380 170 ma ma f rxifclk = 45.056 mhz f rxifclk = 20 mhz i dd supply current, operational (transmitter only, f rxifclk = 0 mhz) 20 9 ma ma f txifclk = 45.056 mhz f txifclk = 20 mhz v ih(min) high level input voltage 0.7 x v dd volts logic '1' v il(max) low level input voltage 0.2 x v dd volts logic '0' i ih(min) high level input current 10 m a all inputs, v in = v dd i il(max) low level input current e10 m a txifclk, rxifclk, reset eeeeee only, v in = v ss i il(max) low level input current e130 e45 e15 m a all other inputs, v in = v ss v oh(min) high level output voltage v dd e 0.4 v dd volts i o = e2.0 ma, all outputs v ol(max) low level output voltage 0.2 0.4 volts i o = +2.0 ma, all outputs c in input capacitance 2 pf all inputs c out output capacitance 4 pf all outputs the typical operational supply current under various operating conditions can be calculated from the equation: i dd = 5 x f rxifclk + 13 x f chip ma where f rxifclk is the frequency of rxifclk , and f chip is the chipping rate, both in mhz power = v dd x i dd .com .com .com .com 4 .com u datasheet
STEL-2000A 38 transmitter input/output timing txifclk txin t ch t cl t su t hd t ct t ct txchppls txbitpls, txtrkpls, txacqpls don't care valid don't care txiout, txqout t ct txifout a.c. characteristics operating conditions: v dd = 5.0 v 5%, v ss = 0 v, t a = 0 to 70 c symbol parameter min. max. units conditions f txifclk txifclk frequency (txifout not used) 45.056 20.0 mhz mhz STEL-2000A+45 only STEL-2000A+20 only f txifclk txifclk frequency ( txifout in use) 20 mhz both speed grades t ch txifclk pulse width, high 10 nsec. t cl txifclk pulse width, low 10 nsec. t su txin to txifclk setup 3 nsec. t hd txin to txifclk hold 5 nsec. t ct txifclk to txbitpls , txtrkpls, txacqpls, txiout or txqout delay 35 nsec. notes: 1. the number of txifclk cycles per cycle of txchppls is determined by the data stored in bits 5-0 of address 41 h . it is shown as 2 in the above timing diagram but can be set from 2 to 64. 2. the width of the txbitpls , txtrkpls and txacqpls signal pulses is equal to the period of txchppls; i.e., equal to the pn chip period. 3. in qpsk mode, the txbitpls signal pulses high twice during each symbol period, once during the center chip and once during the last chip. if the number of chips per symbol is even, the number of chip periods between the txbitpls pulse at the end of the previous symbol and the one in the center of the symbol will be one more than the number of chip periods between the txbitpls pulse in the center of the symbol and the one at the end. the falling edge of the second pulse corresponds to the end of the symbol period. 4. the txtrkpls signal pulses high once each symbol period, during the last chip period of that symbol. the falling edge corresponds to the end of the symbol period. .com .com .com .com 4 .com u datasheet
39 STEL-2000A 5. the txacqpls signal pulses high once each burst, transmission, during the last chip of the acquisi- tion/preamble symbol. the falling edge corresponds to the end of this symbol period. receiver input/output timing rxifclk rxiin, rxqin rxsplpls rxsympls t ch t cl t su t hd t cr t cr t cd rxdrdy rxout, rxiout, rxqout a.c. characteristics operating conditions: v dd = 5.0 v 5%, v ss = 0 v, t a = 0 to 70 c, symbol parameter min. max. units conditions f rxifclk rxifclk frequency 45.056 20.0 mhz mhz STEL-2000A+45 only STEL-2000A+20 only t ch rxifclk pulse width, high 10 nsec. t cl rxifclk pulse width, low 10 nsec. t su rxiin or rxqin to rxifclk setup 3 nsec. t hd rxiin or rxqin to rxifclk hold 7 nsec. t cr rxifclk to rxsplpls , rxsympls , or rxdrdy eeeeeeeee delay 35 nsec. t cd rxifclk to rxout , rxiout , or rxqout delay 35 nsec. notes: 1. the number of rxifclk cycles per cycle of rxsplpls is determined by the data stored in bits 5-0 of address 02 h . it is shown as 2 in the above timing diagram but can be set from 2 to 64. 2. the rising edge of rxdrdy eeeeeeeee should be used to clock out the data (rxout , rxiout, or rxqout). .com .com .com .com 4 .com u datasheet
STEL-2000A 40 rxtest bus and microprocessor interface timing write csel addr 6-0 data 7- 0 valid valid valid valid don't care don't care don't care don't care t su t hd t w oen rxtest 7-0 valid hi-z hi-z t zv t vz a.c. characteristics operating conditions: v dd = 5.0 v 5%, v ss = 0 v, t a = 0 to 70 c, symbol parameter min. max. units conditions t su csel eeeee , addr , data to write setup 5 nsec. t hd write to csel eeeee , addr , data hold 5 nsec. t w write pulse width 5 nsec. t zv oen eeee low to rxtest valid 3 12 nsec. t vz oen eeee high to rxtest high impedance 2 8 nsec. .com .com .com .com 4 .com u datasheet
41 STEL-2000A appendix i: theory of operation digital downconversion the STEL-2000A receiver?s downconverter circuitry allows use of two distinct modes, where the mode chosen will depend upon the application. in applica- tions where the received pn chip rate is less than approximately 1 / 8 of the i.f. sample clock ( rxifclk ) rate, the STEL-2000A can be used with a single a/d converter (adc) and operate in direct i.f. sampling mode. for higher chip rate applications, it is neces- sary to use the STEL-2000A in the full quadrature sampling mode; i.e., using a quadrature signal source, two adcs, and the on-chip nco in its quadrature mode. using the STEL-2000A with a single adc in direct i.f. sampling mode direct i.f. sampling mode allows one rather than two adcs to be used, as will be explained below. if appropriate for the application, use of direct i.f. sampling mode can reduce the system cost since quadrature downconversion or splitting and the sec- ond adc used in quadrature sampling mode are not required. the trade-off, however, is in the lower max- imum pn chip rate that can be supported by the STEL-2000A in direct i.f. sampling mode as com- pared to the maximum rate that can be supported by quadrature sampling mode. in direct i.f. sampling mode, the sampled signal is presented as input to the receiver?s i channel input ( rxiin) and the q channel input ( rxqin ) is held to zero (where zero is defined by the adc input for- mat ). as a result, only two of the four multipliers in the downconverter?s complex multiplier are used and the device does not make a true single-sideband downconversion from i.f. to baseband. in quadra- ture sampling mode, by contrast, quadrature inputs to two adcs provide i and q inputs to the stel- 2000a and the full complex multiplier is used. an illustration of the operation of direct i.f. sampling mode is shown in the frequency domain in figure 7, where the spectra have been drawn asymmetrically so that spectral inversions can be readily identified. the spectrum of a real input signal with center (i.f.) frequency of f 1 and signal bandwidth b is shown in line 1 of figure 7. the bandwidth b is the two-sided bandwidth, corresponding to a pn chip rate of 1/ 2 b mcps. note that throughout this discussion it is assumed that the signal bandwidth does not exceed 1/ 2 f sa ; i.e., b < 1/ 2 f sa . otherwise, the mixing and sampling processes to be described will result in destructive in-band aliasing. also, clearly, the i.f. frequency must be able to support the signal band- width; i.e., 1/ 2 b STEL-2000A 42 frequency result in images of the input signal spec- trum at other frequencies, where here the images are centered about multiples of the sampling frequency. in other words, the spectrum of the sampled signal shown in line 3 contains aliases of the input signal at frequencies f 1 n f sa , where n can assume both posi- tive and negative integer values. since the sampling process is linear, no spectral inversion occurs; i.e., the original spectrum is translated along the frequency axis with no mirror reflections of the input spectrum created. the STEL-2000A?s nco provides a quadrature (sine and cosine) output that defines a complex signal. line 4 shows its spectrum as an impulse at frequency -f 1 , where the minus sign reflects the signal?s use in downconversion and the absence of a positive impulse at frequency +f 1 results because the nco output is truly complex. aliases of this impulse are shown offset by integer multiples of f sa to reflect the sampled nature of the nco output. when the input sampled signal of line 3 is then modulated with the complex signal of the STEL-2000A?s quadrature nco of line 4, the signal spectrum after mixing is as shown in line 5. the sections shown inside the shaded areas are the aliases of the baseband signal beyond the nyquist frequency and are not of concern. the sig- nals inside the primary baseband nyquist region (|f|< 1/ 2 f sa ) consist of the desired signal and a spectrally reversed or inverted image signal with cen- ter frequency separated from that of the desired signal by 2 f 1 , twice the i.f. frequency before sampling. this image signal can be removed by a subsequent ideal lowpass filter as shown in line 6. in figure 7 the input signal is shown at a low i.f. fre- quency such that f 1 < 1/ 2 f sa ; i.e., the signal is only defined inside the primary nyquist region. provided, however, that b < 1/ 2 f sa , that condition need not be true as long as the input spectrum is only defined for frequencies within a non-primary nyquist region; i.e., defined only over frequencies f such that: (n- 1/ 2 )f sa <|f|<(n+ 1/ 2 )f sa for positive integer values of n. direct i.f. sampling mode with this type of signal is shown in figure 8, where it can be seen that in line 3 the diagram?s high frequency input has the same spectrum after sampling as does the low fre- quency input in figure 7; consequently, all subse- quent operations are identical to those in figure 7. this result stems from the periodic nature of sam- pling: sampling an input frequency f 1 is theoretically indistinguishable from sampling an input frequency (n f sa + f 1 ) for positive integer n and positive f 1 < 1/ 2 f sa . a slightly different result obtains, however, when sampling an input frequency (n f sa - f 1 ), again for positive integer n and positive f 1 < 1/ 2 f sa . in this case, the positions of the spectrally inverted and spec- trally correct aliases will be interchanged when com- pared with an input frequency of (n f sa + f 1 ). as a consequence, the desired baseband signal after down- conversion and filtering will also be spectrally inverted. this phenomenon is equivalent to high-side conversion; i.e., downconversion of a signal by means of a local oscillator at a frequency higher than the car- rier frequency. if the modulation type is qpsk, demodulation of a spectrally inverted signal will result in the inversion of the q channel data (which can be readily corrected); if the modulation type is bpsk, there is no effect on the demodulated data. the above discussion has assumed ideal lowpass fil- tering to recover the desired signal at baseband, but, in the STEL-2000A?s downconverter, an ideal lowpass filter is not available. the quadrature integrate and dump filter of the downconverter serves this purpose instead. the downconverter?s integrate and dump freq. input spectrum bandwidth: b 0 freq. 0 freq. spectrum after a/d 0 spectrum of sampling process 1 2 3 ? sa ?f 1 f sa + f 1 f sa ? sa f sa ? sa ? 1 f 1 figure 8: direct i.f. sampling mode with i.f. frequency (f sa + f 1 ) > sampling frequency f sa .com .com .com .com 4 .com u datasheet
43 STEL-2000A gain db ?0 ?5 ?0 ?5 ?0 ?5 ?0 ? 0 01 2345 nf / f sa figure 9: g( w ) = sin( w ?)/ w ?, where w ? = (2 p nf)/f sa filter is a decimation filter, integrating input samples over a programmable number of sample periods, n, so that the output sampling rate is ( 1 / n ) th of the input sampling rate and the i.f. sampling rate f sa is deci- mated to the baseband sampling rate. since the stel- 2000a?s pn matched filter requires two samples per chip, the baseband sampling rate must be at twice the pn chip rate and n must equal f sa /b. when the sampling rate is much greater than the signal band- width (or, equivalently, the chip rate), the integrate and dump filter is most effective in attenuating the unwanted aliased image. this performance can be seen from the transfer function g( w ) of a decimation filter, where: g( w ) = sin( w ?)/ w ? and w ? = (2 p nf)/f sa . figure 9 shows a plot of the gain of this transfer func- tion as a function of the normalized frequency (nf/f sa ). to effect the desired low pass filter and eliminate the aliased image in the baseband nyquist region appearing in line 5 of figure 7, the attenuation must be suitably high for frequencies greater than, in the worst case, 1/ 2 b. given a defined signal band- width b, however, judicious choice of f 1 and f sa allows a higher break frequency to be chosen, as will be discussed. as an extreme worst case, if f 1 = 1/ 4 f sa and b= 1/ 2 f sa , corresponding to the highest chip rate that can be handled for a given value of f sa , then the break frequency must be 1/ 2 b (equal to 1/ 4 f sa ). in this example, then, n = f sa /b = 2 and the attenuation provided by the integrate and dump filter is given by the curve of figure 9 for values of (n f / f sa ) greater than 1/ 2 . as can be seen, the attenuation will be at least equal to the peak of the corresponding lobe or at least ~13 db. this sidelobe peak is a worst case, and much of the alias energy outside the desired band will be attenuated by more than 13 db. nonetheless, the presence of unattenuated energy from the unwanted alias degrades performance. it is for this reason that direct i.f. sampling mode is only recommended for received pn chip rates less than 1/ 8 f sa ; in other words, for b< 1/ 4 f sa . the attenuation realized by the integrate and dump filter is then further determined by the choice of the i.f. frequency f 1 and the i.f. sampling rate f sa . the choice of the i.f. frequency and sampling rate is crucial so that the unwanted alias of the signal in the baseband nyquist region lies as far as possible from the desired signal to permit maximum attenuation. the optimum separation of the desired signal and the unwanted alias occurs when the alias is centered at the bounds of the baseband nyquist region, |f|= 1 / 2 f sa as shown in figure 10. in this case, the desired signal is equally spaced from the unwanted aliases in both the positive and negative frequency domains and f 1 = 1 / 4 f sa . consider, then, the worst case appropriate for direct i.f. sampling mode. if b< 1/ 4 f sa as has been said to be appropriate for direct i.f. sampling mode, then n=f sa /b=4, the break frequency is 3/ 8 f sa or greater, and the attenua- tion provided by the integrate and dump filter is given by the curve of figure 9 for values of (n f / f sa ) greater than 3/ 2 . here, the attenuation is at least ~21 db, offering much better attenuation of the unwanted alias than in the previous worst case example. fur- ther analysis shows that if the input snr is 15 db, then the alias attenuated by 21 db will reduce the snr by approximately 1 db. freq. spectrum after mixer 2 f 1 f sa ?2 f 1 5 ? sa f sa figure 10: optimum condition for bandpass sampling .com .com .com .com 4 .com u datasheet
STEL-2000A 44 the optimum choice of i.f. frequency discussed above can be extended beyond the primary nyquist region. since an i.f frequency of nf sa + f 1 produces exactly the same result for any value of n, the general condi- tion for optimum separation of the desired signal and the unwanted alias is: f 1 = nf sa + 1 / 4 f sa ; b< 1 / 2 f sa for positive integer n and positive b and f 1 . and, if care is taken to handle the effect of high side conversion, the following i.f. frequencies also fulfill the optimum condition: f 1 = nf sa - 1 / 4 f sa ; b< 1 / 2 f sa for positive integer n and positive b and f 1 . using the STEL-2000A with two adcs in quadrature sampling mode quadrature sampling mode requires that quadrature i and q channel i.f. inputs are sampled by two adcs and input to the STEL-2000A?s downconverter. all four multipliers of the downconverter?s complex multiplier are then used to perform true single side- band downconversion to baseband. quadrature inputs imply that the input signal is complex, and the input signal spectrum shown in line 1 of figure 11 is thus only defined for positive frequencies. as a result, the image alias within the primary nyquist region associated with direct i.f. sampling mode does not appear and does not have to be attenuated by the integrate and dump filter. as in the prior dis- cussion, this analysis holds as long as b < 1/ 2 f sa , 1/ 2 b < f 1 , and the input spectrum is only defined for fre- quencies within a single nyquist region; i.e., defined only over frequencies f such that: (n- 1/ 2 )f sa <|f|<(n+ 1/ 2 )f sa for positive integer values of n. freq. freq. freq. freq. freq. freq. input spectrum bandwidth: b 0 0 spectrum after a/d 0 spectrum after ideal digital low pass filter 0 quadrature nco spectrum 0 spectrum after mixer 0 spectrum of sampling process 1 2 3 4 5 6 ? 1 f sa ? sa f sa ? sa f sa ? sa f sa ? sa f sa ? sa ? 1 f 1 ? 1 f 1 figure 11: spectra of signals in quadrature sampling mode .com .com .com .com 4 .com u datasheet
45 STEL-2000A differential demodulation as noted in the preceding text, computation of the dot and cross products is fundamental to opera- tion of the dpsk demodulator and frequency dis- criminator. let i k and q k represent the i and q chan- nel inputs, respectively, for the k th symbol after downconversion and despreading. the dot and cross products can then be defined as: dot(k) = i k i k-1 + q k q k-1 ; and, cross(k) = q k i k-1 - i k q k-1 . in the complex domain, these products can be seen to have been defined to form the complex conjugate product between two input samples, one symbol apart. let the k th input sample, s in (k), be defined as: s in (k) o i(k) + j q(k), where i(k) and q(k) are the 8-bit peak power pn matched filter i and q channel outputs directed to the dpsk demodulator. in polar form, s in (k) may be conveniently defined as: s in (k) o a(k).e j(k) with a(k) o i 2 (k)+q 2 (k) (k) o arctan ? ? ? q(k) i(k) . simple substitution then shows that the complex conjugate product between consecutive symbols (with an arbitrary phase shift introduced to the previous symbol value) may be expressed as:: s out (k) = s in (k) . [s in (ke1) . w fixed ] * o dot(k) + j cross(k) where w fixed = arbitrary fixed phase rotation; dot(k) = re[s out (k)]; and, cross(k) = im[s out (k)]. the fixed phase rotation w fixed has been introduced to later simplify the decision criteria, but the ability to express real and imaginary parts of the complex con- jugate product between consecutive symbols with the dot and cross products is the key to their use in dpsk demodulation. bpsk demodulation in dpsk, the phase difference between successive samples is due to the data modulation phase differ- ences, d mod , plus any induced phase rotation between symbols, d rot , resulting from, for example, a frequency offset between the received signal?s i.f. and that provided by the downconverter. for dbpsk, the data modulation differences d mod can take only the values of 0 or 180 . expressing the complex phase difference [(k)-(k-1)] in terms of these components, the decision can be seen to be based on: s out (k) = a(k).a(k-1).e j(k). e -j(k-1) = a(k).a(k-1).e j[ d mod (k) + d rot (k) ] for dbpsk, only the real part of s out (k), dot(k), is needed to determine the modulated phase transition: dot(k) = a(k).a(k-1).cos( d mod (k)+ d rot (k)) = a(k).a(k-1).cos( d rot (k)) where the sign is determined by the transmitted data since cos[ d mod (k)] = 1. as a result, dot(k) ? a 2 (k) if the amplitude of the signal is constant for consecu- tive symbols and if the phase rotation d rot (k) between symbols is small. the STEL-2000A dpsk demodulator can thus use the sign of the dot product in order to make dbpsk symbol decisions without the introduction of any fixed phase rotation. qpsk demodulation for dqpsk modulation, the possible phase shifts between successive symbols due to the modulation are 0 , 90 , 180 , and 270 . here, introduction of a phase shift ( w fixed ) of 45 to the previous symbol in the calculation of the dot and cross products is desired in order shift the possible phase differences to 45 , 135 , 225 , or 315 so that the dqpsk decision boundaries coincide with the signs of the dot and cross products. in the STEL-2000A dpsk demodula- tor, phase rotation is accomplished in the signal rota- tion block by the following transformation of the i and q channel values:: i rot (k) = [ i(k) - q(k) ]/2 for 45 rotation i rot (k) = [ i(k) + q(k) ]/2 for -45 rotation q rot (k) = [ i(k) + q(k) ]/2 for 45 rotation q rot (k) = -[ i(k) + q(k) ]/2 for -45 rotation the divide by 2 is part of the signal rotation function. this transformation is equivalent to multiplying by (1 j)/2 or (1/ ? 2)ej (fixed) where fixed is 45 . in this case, s out (k) becomes: s out (k) = a(k).a(k-1).e j(k). e -j(k-1). [ w fixed ] * = a(k).a(k-1).e j[ d mod (k) + d rot (k) ]. (1/ ? 2)ej (fixed) .com .com .com .com 4 .com u datasheet
STEL-2000A 46 so that dot(k) ? (1/ ? 2)a(k).a(k-1).cos( d mod (k) - fixed ) cross(k) ? (1/ ? 2)a(k).a(k-1).sin( d mod (k) - fixed ) where the phase rotation d rot (k) due to the fre- quency offset between symbols has been assumed negligible. a summary of the dot(k) and cross(k) products for the possible values of d mod (k) and fixed is shown below, illustrating how the sign of the dot and cross products allow the symbol decision to be made: fixed = -45 fixed = +45 d mod (k) dot(k) cross(k ) dot(k) cross(k ) 0 +a 2 +a 2 +a 2 -a 2 90 -a 2 +a 2 +a 2 +a 2 180 -a 2 -a 2 -a 2 +a 2 270 +a 2 -a 2 -a 2 -a 2 table 25. dot and cross product summary dqpsk demodulation the STEL-2000A dpsk demodulator decision logic is designed so that correct dqpsk decisions are made with a signal rotation of fixed =-45 . for p /4 qpsk modulation, however, the modulator itself inserts 45 between consecutive symbols, and the possible phase shifts between successive symbols due to modulation are 45 , 135 , 225 , and 315 . as a result, the dpsk demodulator should be configured for p /4 qpsk with fixed =0 . frequency error signal generation the frequency discriminator function or error signal can similarly be generated based on the dot and cross products. the objective is an error signal reflecting the sine of the phase difference between the present and prior symbol after correcting for the estimated phase increments due to data modulation. in the STEL-2000A frequency discriminator, the frequency error is calculated through a decision-directed cross- product algorithm and is then used with the loop fil- ter to correct the nco frequency. assuming an input s in (k), where: s in (k) = i(k) + j q(k), the algorithm calculates the frequency discriminator function for dbpsk, s afc/bpsk (k), as: s afc/bpsk (k) = sign[dot(k)] . cross(k) = sign[dot(k)] . a(k).a(k-1).sin((k)-(k-1)) = sign[dot(k)].a(k).a(k-1).sin( d mod (k)+ d rot (k)) ? sign[dot(k)] . a 2 (k).cos[ d mod (k)].sin[ d rot (k)] ? a 2 (k).sin[ d rot (k)]. the final result assumes that the amplitude of the sig- nal is constant over consecutive symbols and shows that the discriminator function is directly related to the change in phase between successive symbols. since the interval between successive symbols is fixed, the discriminator function can be interpreted as a frequency error signal. for dqpsk signals, the STEL-2000A computes the discriminator function s afc/qpsk (k) as: s afc/qpsk (k) = sign[dot(k)].cross(k).sign[cross(k)].dot(k) where the above expression can be reduced to the same as for dbpsk, s afc/qpsk (k) ? a 2 (k).sin( d rot (k)). .com .com .com .com 4 .com u datasheet
47 STEL-2000A using the modulator in the STEL-2000A transmitter the STEL-2000A incorporates a direct digital synthe- sizer (dds) based bpsk/qpsk modulator which can be used to generate the transmit output signal at some if frequency, thereby eliminating the need for a sepa- rate modulator. because it is a sampled data system, like the other parts of the system, care must be taken to ensure that the results of aliasing do not adversely affect the transmit signal. the sampling clock for the modulator is f rxifclk , since the nco is driven by this clock, and for this reason both txifclk and rxifclk must be common when the modulator is being used. when a dds is used to generate an un- modulated signal the results are easy to predict because the stepped sinewave generated by the dds has spectral lines at the frequencies n.f clk f out for all integer values of n. however, when the dds sig- nal is modulated with a series of rectangular pulses each one of these spectral lines is replaced by a sinc function (i.e., sin(x)/x), the spectrum of the modulat- ing signal itself, each with a very significant band- width. any part of the spectrum of the baseband component (i.e. the one where n = 0 in the equation n.f clk f out ) above the nyquist frequency (f clk /2) results in its first alias (i.e. the one where n = 1 in the equation n.f clk f out ) intruding below the nyquist frequency, and this may interfere with the desired signal. this is called aliasing distortion. a typical example is shown in figure 12. the baseband component is shown as a the thick curve and the first alias is shown as the lighter curve; the higher order aliases are ignored for simplicity. note that in this example the nulls between the side- lobes of the baseband signals coincide with those of the first alias; this is simply the result of the numbers chosen, and this will not occur in all cases. in a practi- cal system the output signal would typically be fil- tered to eliminate the sidelobes, as well as the signals above the nyquist frequency. as can be seen, the second and third sidelobes of the first alias fall right into this band of the spectrum, distorting the desired signal. the magnitude of this signal at the peak of the sidelobes is approximately e18 dbc. clearly some improvement can be obtained by choosing a carrier frequency that increases the separation of the base- band main lobe from the first alias main lobe, as shown in figure 13. nyquist frequency 2 x c r 0 ?3 ?8 ?1 ?3 ?5 db frequency/f txifclk 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 figure 12: spectrum of dds modulated at 0.1 x f rxifclk when carrier frequency is set to 0.4 x f rxifclk nyquist frequency 0 ?3 ?8 ?1 ?3 ?5 db frequency/f txifclk 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2 x c r figure 13: spectrum of dds modulated at 0.1 x f rxifclk when carrier frequency is set to 0.25 x f rxifclk .com .com .com .com 4 .com u datasheet
STEL-2000A 48 in this case the carrier frequency has been reduced to 0.25 x f rxifclk and now the fourth and fifth sidelobes of the first alias fall in the same part of the spectrum as the baseband main lobe, reducing the distortion to approximately e23 dbc at the peak of the sidelobe. in both of the cases shown above, especially the sec- ond, the level of the distortion is low enough that the performance penalty would not be very great since the effective distortion is reduced by the processing gain in the despreader. however, in both of these cases the chipping rate was a very modest 10% of the frequency of the system clocks; if the chipping rate is increased to 40% the situation is very different, as shown in figure 14. here, both the chipping rate and the carrier frequency have been set at 20% of the clock frequency and now the baseband main lobe straddles the nyquist fre- quency. consequently, the first alias of the main lobe overlaps the spectrum of the baseband main lobe, resulting in very sig nificant aliasing distortion which cannot be eliminated by filtering. this would severely effect the performance of the system and in general will be completely unacceptable. reducing the carrier frequency to 25% of the clock dramatically reduces the distortion level again, as shown in figure 15. although the distortion is still fairly severe, adequate performance may still be obtainable as a result of the processing gain, but the performance would be many dbs off the theoretical limit. the conclusion is that as the chipping rate of the system increases so does the effect of the aliasing distortion in the modulator, and the performance will degrade. a practical limit may be in the region of 15% of the clock frequency, but in reality every case is unique and should be evaluated before deciding to use the internal dds modulator. nyquist frequency 0 ?3 ?8 ?1 ?3 ?5 db frequency/f txifclk 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2 x c r figure 14: spectrum of dds modulated at 0.4 x f rxifclk when carrier frequency is set to 0.4 x f rxifclk 0 db nyquist frequency frequency/f txifclk 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ?3 ?8 ?1 ?3 ?5 0 2 x c r figure 15: spectrum of dds modulated at 0.4 x f rxifclk when carrier frequency is set to 0.25 x f rxifclk .com .com .com .com 4 .com u datasheet
49 STEL-2000A appendix ii: typical application spread spectrum bpsk/qpsk transceiver STEL-2000A lpf a/d rf tr a ns- ceiver fixed oscillator (up/down converter) data out data in tx clock 4x tx chip clock rx clock 4x rx clock linear rf module rxiin t xifout r x ifc lk rxiout rxdrdy txin txbitpls txifclk rxqout lpf d/a 8 8 baseband module figure 16: spread spectrum bpsk/qpsk transceiver .com .com .com .com 4 .com u datasheet

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